-
公开(公告)号：US20160087918A1
公开(公告)日：2016-03-24
申请号：US14494190
申请日：2014-09-23
Applicant: Intel Corporation
Inventor： Roger K. Cheng , Stefan Rusu , Aaron Martin
IPC: H04L12/931 , G06F17/50
CPC classification number: G06F17/5063 , G06F2217/78 , H03M1/12 , H03M1/66
Abstract: Described is an apparatus which comprises: logic to convert output of at least one sensor to a digital sensing signal; a router coupled to the sensor, the router to receive the digital sensing signal and to map into circuit data; and one or more communication interfaces, coupled to the router, to forward circuit data to a circuit endpoint. Described is a method which comprises: providing one or more digital sensing signals from a plurality of sensors; receiving the one or more digital sensing signals; generating packets of data using the one or more digital sensing signals; and providing the packets of data to one or more destinations.
Abstract translation: 描述了一种装置，其包括：将至少一个传感器的输出转换为数字感测信号的逻辑; 路由器耦合到传感器，路由器接收数字感测信号并映射到电路数据中; 以及耦合到路由器的一个或多个通信接口，以将电路数据转发到电路端点。 描述了一种方法，其包括：从多个传感器提供一个或多个数字感测信号; 接收一个或多个数字感测信号; 使用所述一个或多个数字感测信号产生数据包; 并将数据包提供给一个或多个目的地。
-
Patent Agency Ranking
公开(公告)号：US10672438B2
公开(公告)日：2020-06-02
申请号：US16147635
申请日：2018-09-29
Applicant: Intel Corporation
Inventor： Mohammed G. Mostofa , Roger K. Cheng , Aaron Martin , Christopher Mozak , Pavan Kumar Kappagantula , Hsien-Pao Yang
IPC: G11C7/10 , G06F1/3234 , G06F13/16
Abstract: An apparatus is provided which comprises: a first circuitry to sample a first input signal to generate a first sampled signal, and to sample a second input signal to generate a second sampled signal, wherein the first input signal comprises data; a second circuitry to receive the first sampled signal and the second sampled signal, and to generate a first pair of differential signals; an offset cancellation circuitry to cancel or reduce an offset in the first pair of differential signals; and a latch to receive the first pair of differential signals subsequent to the cancellation or reduction of the offset, and to output a second pair of differential signals, wherein the second pair of differential signals is indicative of the data.
-
公开(公告)号：US10007749B2
公开(公告)日：2018-06-26
申请号：US14494190
申请日：2014-09-23
Applicant: Intel Corporation
Inventor： Roger K. Cheng , Stefan Rusu , Aaron Martin
CPC classification number: G06F17/5063 , G06F2217/78 , H03M1/12 , H03M1/66
Abstract: Described is an apparatus which comprises: logic to convert output of at least one sensor to a digital sensing signal; a router coupled to the sensor, the router to receive the digital sensing signal and to map into circuit data; and one or more communication interfaces, coupled to the router, to forward circuit data to a circuit endpoint. Described is a method which comprises: providing one or more digital sensing signals from a plurality of sensors; receiving the one or more digital sensing signals; generating packets of data using the one or more digital sensing signals; and providing the packets of data to one or more destinations.
-
公开(公告)号：US11023244B2
公开(公告)日：2021-06-01
申请号：US15713974
申请日：2017-09-25
Applicant: Intel Corporation
Inventor： Ee Loon Teoh , Eng Hun Ooi , Roger K. Cheng
Abstract: In one embodiment, a link training controller is to train a link. The link training controller may be configured to: update a first link parameter of a link setting for the link to a first value; write data to the memory; read the data from the memory using the first value of the first link parameter; and in response to a determination that the data read from the memory does not match the data written to the memory, send an in-band link recovery command to the memory via the link to cause the memory to participate in a link recovery protocol with the apparatus. Other embodiments are described and claimed.
-
公开(公告)号：US10923164B2
公开(公告)日：2021-02-16
申请号：US16147634
申请日：2018-09-29
Applicant: Intel Corporation
Inventor： Hariprasath Venkatram , Mohammed G. Mostofa , Rajesh Inti , Roger K. Cheng , Aaron Martin , Christopher Mozak , Pavan Kumar Kappagantula , Hsien-Pao Yang , Mozhgan Mansuri , James Jaussi , Harishankar Sridharan
IPC: G11C7/10 , G06F1/3234 , G06F13/16
Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply; second and third power supply rails to provide second and third power supplies, respectively, wherein a voltage level of the first power supply is higher than a voltage level of each of the second and third power supplies; a first driver circuitry coupled to the first power supply rail and the second power supply rail; a second driver circuitry coupled to the third power supply rail, and coupled to the first driver circuitry; and a stack of transistors of N conductivity type coupled to the first power supply rail, and to the second driver circuitry.
-
公开(公告)号：US20200105319A1
公开(公告)日：2020-04-02
申请号：US16147635
申请日：2018-09-29
Applicant: Intel Corporation
Inventor： Mohammed G. Mostofa , Roger K. Cheng , Aaron Martin , Christopher Mozak , Pavan Kumar Kappagantula , Hsien-Pao Yang
Abstract: An apparatus is provided which comprises: a first circuitry to sample a first input signal to generate a first sampled signal, and to sample a second input signal to generate a second sampled signal, wherein the first input signal comprises data; a second circuitry to receive the first sampled signal and the second sampled signal, and to generate a first pair of differential signals; an offset cancellation circuitry to cancel or reduce an offset in the first pair of differential signals; and a latch to receive the first pair of differential signals subsequent to the cancellation or reduction of the offset, and to output a second pair of differential signals, wherein the second pair of differential signals is indicative of the data.
-
-
-
-
-
Search Results
6
records
(took 0.015 seconds)
