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1.发明授权公开(公告)号：US11070200B2
公开(公告)日：2021-07-20
申请号：US16144949
申请日：2018-09-27
Applicant: Intel Corporation
Inventor： Aaron Martin , Roger Cheng , Hari Venkatramani , Navneet Dour , Mozhgan Mansuri , Bryan Casper , Frank O'Mahony , Ganesh Balamurugan , Ajay Balankutty , Kuan Zhou , Sridhar Tirumalai , Krishnamurthy Venkataramana , Alex Thomas , Quoc Nguyen
Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.
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公开(公告)号：US10134463B2
公开(公告)日：2018-11-20
申请号：US15727850
申请日：2017-10-09
Applicant: Intel Corporation
Inventor： Mozhgan Mansuri , Aaron Martin , James A. McCall
Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.
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公开(公告)号：US20180102162A1
公开(公告)日：2018-04-12
申请号：US15727850
申请日：2017-10-09
Applicant: Intel Corporation
Inventor： Mozhgan Mansuri , Aaron Martin , James A. McCall
CPC classification number: G11C11/4076 , G06F1/10 , G06F13/4234 , G11C7/10 , G11C7/1087 , G11C7/222 , G11C11/4093 , H03K5/14 , H03K2005/00052 , H04L7/0337
Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.
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4.发明申请公开(公告)号：US20160259354A1
公开(公告)日：2016-09-08
申请号：US14638928
申请日：2015-03-04
Applicant: Intel Corporation
Inventor： Moonkyun Maeng , Aaron Martin
Abstract: Described is an apparatus which comprises: a first feedback loop to generate a control signal for regulating an output voltage provided to a load; and a second feedback loop, separate from the first feedback loop, to receive the control signal from the first feedback loop, the second feedback loop to regulate the output voltage provided to the load.
Abstract translation: 描述了一种装置，其包括：第一反馈环路，用于产生用于调节提供给负载的输出电压的控制信号; 以及与第一反馈回路分开的第二反馈回路，以从第一反馈回路接收控制信号，第二反馈回路用于调节提供给负载的输出电压。
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5.发明授权公开(公告)号：US09355693B2
公开(公告)日：2016-05-31
申请号：US13830637
申请日：2013-03-14
Applicant: Intel Corporation
Inventor： Moonkyun Maeng , Aaron Martin , Hsiao-Ching Chuang
CPC classification number: G11C7/1084
Abstract: Embodiments include systems, methods, and apparatuses for reading a data signal from a memory, such as a dynamic random access memory (DRAM). In one embodiment, a memory receiver may include a differential amplifier to receive a data signal from the memory and pass a differential output signal based on a voltage difference between the data signal and a reference voltage. The data signal may have a first direct current (DC) average voltage level, and the differential amplifier may shift the differential output signal to a second DC average voltage level that is substantially constant over a range of values of the first DC average voltage level. In another embodiment, a voltage offset compensation (VOC) circuit may apply a compensation voltage to the output signal that is based on an activated rank or an identity of the memory module. Other embodiments may be described and claimed.
Abstract translation: 实施例包括用于从诸如动态随机存取存储器（DRAM）的存储器读取数据信号的系统，方法和装置。 在一个实施例中，存储器接收器可以包括差分放大器，以从存储器接收数据信号，并且基于数据信号和参考电压之间的电压差传递差分输出信号。 数据信号可以具有第一直流（DC）平均电压电平，并且差分放大器可以将差分输出信号移位到在第一直流平均电压电平的值的范围内基本上恒定的第二直流平均电压电平。 在另一个实施例中，电压偏移补偿（VOC）电路可以对基于激活的等级或存储器模块的标识的输出信号施加补偿电压。 可以描述和要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US09024665B2
公开(公告)日：2015-05-05
申请号：US13801759
申请日：2013-03-13
Applicant: Intel Corporation
Inventor： Derek M. Conrow , Aaron Martin , James A. McCall
CPC classification number: H04B1/0475 , H03K19/018521 , H03K19/018585 , H03K19/018592 , H04L25/0278
Abstract: Described is an integrated circuit (IC) which comprises: an input-output (I/O) pad for coupling to a transmission line; a voltage mode driver coupled to the I/O pad, the voltage mode driver having a pull-up driver and a pull-down driver; and a current mode driver coupled to the I/O pad, the current mode driver operable to function in parallel to the voltage mode driver.
Abstract translation: 描述了一种集成电路（IC），其包括：用于耦合到传输线的输入 - 输出（I / O）焊盘; 耦合到I / O焊盘的电压模式驱动器，具有上拉驱动器和下拉驱动器的电压模式驱动器; 以及耦合到所述I / O焊盘的电流模式驱动器，所述电流模式驱动器可操作以与所述电压模式驱动器并联起作用。
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7.发明申请公开(公告)号：US20210320652A1
公开(公告)日：2021-10-14
申请号：US17357456
申请日：2021-06-24
Applicant: Intel Corporation
Inventor： Aaron Martin , Roger Cheng , Hari Venkatramani , Navneet Dour , Mozhgan Mansuri , Bryan Casper , Frank O'Mahony , Ganesh Balamurugan , Ajay Balankutty , Kuan Zhou , Sridhar Tirumalai , Krishnamurthy Venkataramana , Alex Thomas , Quoc Nguyen
Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.
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公开(公告)号：US10923164B2
公开(公告)日：2021-02-16
申请号：US16147634
申请日：2018-09-29
Applicant: Intel Corporation
Inventor： Hariprasath Venkatram , Mohammed G. Mostofa , Rajesh Inti , Roger K. Cheng , Aaron Martin , Christopher Mozak , Pavan Kumar Kappagantula , Hsien-Pao Yang , Mozhgan Mansuri , James Jaussi , Harishankar Sridharan
IPC: G11C7/10 , G06F1/3234 , G06F13/16
Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply; second and third power supply rails to provide second and third power supplies, respectively, wherein a voltage level of the first power supply is higher than a voltage level of each of the second and third power supplies; a first driver circuitry coupled to the first power supply rail and the second power supply rail; a second driver circuitry coupled to the third power supply rail, and coupled to the first driver circuitry; and a stack of transistors of N conductivity type coupled to the first power supply rail, and to the second driver circuitry.
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公开(公告)号：US20200105319A1
公开(公告)日：2020-04-02
申请号：US16147635
申请日：2018-09-29
Applicant: Intel Corporation
Inventor： Mohammed G. Mostofa , Roger K. Cheng , Aaron Martin , Christopher Mozak , Pavan Kumar Kappagantula , Hsien-Pao Yang
Abstract: An apparatus is provided which comprises: a first circuitry to sample a first input signal to generate a first sampled signal, and to sample a second input signal to generate a second sampled signal, wherein the first input signal comprises data; a second circuitry to receive the first sampled signal and the second sampled signal, and to generate a first pair of differential signals; an offset cancellation circuitry to cancel or reduce an offset in the first pair of differential signals; and a latch to receive the first pair of differential signals subsequent to the cancellation or reduction of the offset, and to output a second pair of differential signals, wherein the second pair of differential signals is indicative of the data.
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公开(公告)号：US09786353B2
公开(公告)日：2017-10-10
申请号：US15047427
申请日：2016-02-18
Applicant: Intel Corporation
Inventor： Mozhgan Mansuri , Aaron Martin , James A. McCall
CPC classification number: G11C11/4076 , G06F1/10 , G06F13/4234 , G11C7/10 , G11C7/1087 , G11C7/222 , G11C11/4093 , H03K5/14 , H03K2005/00052 , H04L7/0337
Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.
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