公开(公告)号：US20220365869A1

公开(公告)日：2022-11-17

申请号：US17456583

申请日：2021-11-25

Applicant: Intel Corporation

Inventor： Subinlal PK ,  Keith JONES ,  Rolf KUEHNIS

IPC: G06F11/36

Abstract: A debug test system is provided. The debug test system includes one or more interfaces configured to communicate with a target system and processing circuitry configured to control the one or more interfaces. Further, the processing circuitry is configured to receive information about an operation state of the target system from the target system and to generate control information for the target system to adjust a debug session on the target system. The processing circuitry is further configured to transmit the control information to the target system.

公开(公告)号：US20250110175A1

公开(公告)日：2025-04-03

申请号：US18374198

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Rakesh KANDULA ,  Sankaran M. MENON ,  Rolf KUEHNIS

IPC: G01R31/319 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185

Abstract: Methods, apparatus, and computer programs are disclosed to detect computing system hardware defects using a portable storage device. In one embodiment, a method includes accessing a portable storage device to obtain an identifier and a set of test patterns to test a set of circuits of a computing system, the identifier to map to the set of test patterns. The method further includes determining that the set of test patterns is to be executed on the computing system based on the identifier to be obtained from accessing the portable storage device. Responsive to the determination, and executing the set of test patterns loaded from the portable storage device on the set of circuits of the computing system to detect one or more hardware defects of the set of circuits.

公开(公告)号：US20240103077A1

公开(公告)日：2024-03-28

申请号：US17954658

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Rakesh KANDULA ,  Sankaran MENON ,  Rolf KUEHNIS

IPC: G01R31/3185 ,  G01R31/319

CPC classification number: G01R31/318533 ,  G01R31/31907 ,  G01R31/31924

Abstract: Time to read the data registers in a remote Test Access Port (TAP) in a subsystem in a System-on-Chip (SoC) is reduced by reading multiple data registers in remote Test Access Ports in parallel. A Test Access Port Bridge provides access to multiple same width data registers in parallel. The same width data registers can be for the same function or different functions. The subsystems with a remote Test Access Port in the SoC can include Peripheral Component Interconnect Express (PCIe), Voltage Droop Monitors (VDMs), In-Die Variation (IDV) Monitor fub-lets, Temperature Sensors, Performance Monitors and telemetry subsystems.