公开(公告)号：US10002654B2

公开(公告)日：2018-06-19

申请号：US14752464

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Jaydeep P Kulkarni ,  Pramod Kolar ,  Ankit Sharma ,  Subho Chatterjee ,  Karthik Subramanian ,  Farhana Sheikh ,  Wei-Hsiang Ma

IPC: G11C8/08 ,  G11C7/18 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419 ,  G11C5/14

CPC classification number: G11C8/08 ,  G11C5/145 ,  G11C7/18 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419

Abstract: In some embodiments, disclosed is a wordline boosting technique using a self-timed capacitive charge boosting approach.

公开(公告)号：US09812189B2

公开(公告)日：2017-11-07

申请号：US14731319

申请日：2015-06-04

Applicant: Intel Corporation

Inventor： Pramod Kolar ,  Wei-Hsiang Ma ,  Gunjan H. Pandya

IPC: G11C11/00 ,  G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418

Abstract: An apparatus is provided which comprises: a memory array; first logic to detect whether first and second word-lines (WL) for a row of the memory array are active; and second logic to deactivate one of the first and second WLs such that one of the first and second WLs is active for the row.

公开(公告)号：US20160358643A1

公开(公告)日：2016-12-08

申请号：US14731319

申请日：2015-06-04

Applicant: Intel Corporation

Inventor： Pramrod Kolar ,  Wei-Hsiang Ma ,  Gunjan H. Pandya

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418

Abstract: An apparatus is provided which comprises: a memory array; first logic to detect whether first and second word-lines (WL) for a row of the memory array are active; and second logic to deactivate one of the first and second WLs such that one of the first and second WLs is active for the row.

Abstract translation: 提供了一种装置，包括：存储器阵列; 用于检测存储器阵列的行的第一和第二字线（WL）是否处于活动状态的第一逻辑; 以及第二逻辑，用于停用所述第一和第二WL中的一个，使得所述第一和第二WL中的一个对于所述行是活动的。