公开(公告)号：US20170010648A1

公开(公告)日：2017-01-12

申请号：US15270206

申请日：2016-09-20

Applicant: Intel Corporation

Inventor： Shaun M. Conrad ,  William Knolla ,  Douglas R. Moran ,  Sm M. Rahman ,  Jawad Haj-Yihia ,  Alon Naveh ,  Ohad Falik

IPC: G06F1/32 ,  G06F13/40

CPC classification number: G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F13/40 ,  G06F13/4027 ,  G06F13/4068 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/172

Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.

Abstract translation: 处理器包括至少一个核心，功率控制单元和与外围控制器耦合的第一互连。 第一互连是提供用于从处理器到外围控制器的第一电力管理数据的通信的第一单向通信路径。 描述和要求保护其他实施例。

公开(公告)号：US10157160B2

公开(公告)日：2018-12-18

申请号：US14865005

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Michael T. Klinglesmith ,  Mikal C. Hunsaker ,  William Knolla ,  Hartej Singh

IPC: G06F13/00 ,  G06F13/14 ,  G06F3/00 ,  G06F13/42 ,  G06F13/20 ,  G06F13/40

Abstract: In one embodiment, a method includes: receiving, via a sideband interface of a multi-root agent associated with a first root space and a second root space, a reset prepare signal to inform the multi-root agent that the first root space is to be reset; sending, via the sideband interface, an acknowledgement signal to acknowledge the reset prepare signal; receiving one or more transactions for the first root space from a fabric coupled to the multi-root agent; and terminating the one or more transactions responsive to the reset prepare signal, where the first root space is in a reset state when the one or more transactions are received. Other embodiments are described and claimed.

公开(公告)号：US09766683B2

公开(公告)日：2017-09-19

申请号：US15270206

申请日：2016-09-20

Applicant: Intel Corporation

Inventor： Shaun M. Conrad ,  William Knolla ,  Douglas R. Moran ,  Sm M. Rahman ,  Jawad Haj-Yihia ,  Alon Naveh ,  Ohad Falik

IPC: G06F13/40 ,  G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F13/40 ,  G06F13/4027 ,  G06F13/4068 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/172

Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.

公开(公告)号：US09690353B2

公开(公告)日：2017-06-27

申请号：US13799524

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Douglas Moran ,  Achmed Rumi Zahir ,  William Knolla ,  Hartej Singh ,  Vasudev Vasu Bibikar ,  Sanjeev Jahagirdar ,  Michael Klinglesmith ,  Irwin Vaz ,  Varghese George

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.

公开(公告)号：US09477627B2

公开(公告)日：2016-10-25

申请号：US13727052

申请日：2012-12-26

Applicant: Intel Corporation

Inventor： Shaun M. Conrad ,  William Knolla ,  Douglas R. Moran ,  SM M. Rahman ,  Jawad Haj-Yihia ,  Alon Naveh ,  Ohad Falik

IPC: G06F13/40 ,  G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F13/40 ,  G06F13/4027 ,  G06F13/4068 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/172

Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.

Abstract translation: 处理器包括至少一个核心，功率控制单元和与外围控制器耦合的第一互连。 第一互连是提供用于从处理器到外围控制器的第一电力管理数据的通信的第一单向通信路径。 描述和要求保护其他实施例。

公开(公告)号：US20160357696A1

公开(公告)日：2016-12-08

申请号：US14865005

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Michael T. Klinglesmith ,  Mikal C. Hunsaker ,  William Knolla ,  Hartej Singh

IPC: G06F13/40

CPC classification number: G06F13/4068

Abstract: In one embodiment, a method includes: receiving, via a sideband interface of a multi-root agent associated with a first root space and a second root space, a reset prepare signal to inform the multi-root agent that the first root space is to be reset; sending, via the sideband interface, an acknowledgement signal to acknowledge the reset prepare signal; receiving one or more transactions for the first root space from a fabric coupled to the multi-root agent; and terminating the one or more transactions responsive to the reset prepare signal, where the first root space is in a reset state when the one or more transactions are received. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种方法包括：经由与第一根空间和第二根空间相关联的多根代理的边带接口接收复位准备信号以通知多根代理第一根空间为 复位; 通过边带接口发送确认复位准备信号的确认信号; 从耦合到所述多根代理的结构接收用于所述第一根空间的一个或多个事务; 以及响应于重置准备信号终止一个或多个事务，其中当接收到一个或多个事务时，第一根空间处于复位状态。 描述和要求保护其他实施例。