公开(公告)号：US20170337131A1

公开(公告)日：2017-11-23

申请号：US15671952

申请日：2017-08-08

Applicant: Intel Corporation

Inventor： KRISHNAKANTH V. SISTLA ,  YEN-CHENG LIU ,  ZHONG-NING CAI ,  JEFFREY D. GILBERT

IPC: G06F12/084 ,  G06F12/0815

CPC classification number: G06F12/084 ,  G06F12/0815

Abstract: Preventing request conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to manage request conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches shared amongst a set of cores or processors or agents.

公开(公告)号：US20230169032A1

公开(公告)日：2023-06-01

申请号：US18102568

申请日：2023-01-27

Applicant: Intel Corporation

Inventor： NEVINE NASSIF ,  YEN-CHENG LIU ,  KRISHNAKANTH V. SISTLA ,  GERALD PASDAST ,  SIVA SOUMYA EACHEMPATI ,  TEJPAL SINGH ,  ANKUSH VARMA ,  MAHESH K. KUMASHIKAR ,  SRIKANTH NIMMAGADDA ,  CARLETON L. MOLNAR ,  VEDARAMAN GEETHA ,  JEFFREY D. CHAMBERLAIN ,  WILLIAM R. HALLECK ,  GEORGE Z. CHRYSOS ,  JOHN R. AYERS ,  DHEERAJ R. SUBBAREDDY

IPC: G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F1/04 ,  G06F1/12 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

CPC classification number: G06F15/7889 ,  G06F1/10 ,  G06F15/167 ,  G06F1/04 ,  G06F1/12 ,  G06F9/3869 ,  G06F9/5038 ,  G06F15/17312

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US20200334196A1

公开(公告)日：2020-10-22

申请号：US16917888

申请日：2020-06-30

Applicant: Intel Corporation

Inventor： NEVINE NASSIF ,  YEN-CHENG LIU ,  KRISHNAKANTH V. SISTLA ,  GERALD PASDAST ,  SIVA SOUMYA EACHEMPATI ,  TEJPAL SINGH ,  ANKUSH VARMA ,  MAHESH K. KUMASHIKAR ,  SRIKANTH NIMMAGADDA ,  CARLETON L. MOLNAR ,  VEDARAMAN GEETHA ,  JEFFREY D. CHAMBERLAIN ,  WILLIAM R. HALLECK ,  GEORGE Z. CHRYSOS ,  JOHN R. AYERS ,  DHEERAJ R. SUBBAREDDY

IPC: G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US20150127962A1

公开(公告)日：2015-05-07

申请号：US14598454

申请日：2015-01-16

Applicant: Intel Corporation

Inventor： YEN-CHENG LIU ,  P. KEONG OR ,  KRISHNAKANTH V. SISTLA ,  GANAPATI SRINIVASA

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3243 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0811 ,  G06F15/80 ,  G06F2212/283 ,  G11C7/1072 ,  G11C7/1075 ,  Y02D10/16

Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

Abstract translation: 公开了一种监视架构事件的方法和装置。 架构事件通过推送总线机制链接在一起，每个架构事件都具有指定的时隙。 在每个核心中至少有一个分支的推送总线。 推送总线的每个分支可以监视一个核心与所有的架构事件。 然后将通过推送总线从事件收集的所有数据发送到电源控制单元。