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1.发明授权公开(公告)号：US10432173B2
公开(公告)日：2019-10-01
申请号：US15811851
申请日：2016-06-08
Applicant: Intel IP Corporation
Inventor： Thomas Bauernfeind , Andreas Menkhoff , Michael Bruennert
Abstract: An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.
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2.发明授权System and method for generating a data dependent clock for a DAC in a modulator 有权用于在调制器中为DAC生成数据相关时钟的系统和方法公开(公告)号：US09197258B1
公开(公告)日：2015-11-24
申请号：US14303945
申请日：2014-06-13
Applicant: Intel IP Corporation
Inventor： Andreas Menkhoff , Michael Bruennert , Markus Schimper
CPC classification number: H04B1/0475 , H04L27/20 , H04L27/361
Abstract: A modulator and associated method includes a calculation block configured to receive a plurality of digital samples of a modulated baseband signal, and determine time instances associated with predetermined phase crossings of the modulated baseband signal. The modulator further includes a converter circuit configured to generate a data dependent clock signal having rising and falling edges associated with the determined time instances, and a digital to analog converter configured to receive the data dependent clock signal and generate a square wave output signal having transition times associated with the generated data dependent clock signal.
Abstract translation: 调制器和相关联的方法包括被配置为接收调制基带信号的多个数字样本的计算块，并且确定与调制基带信号的预定相位相关联的时间实例。 调制器还包括转换器电路，其被配置为产生具有与所确定的时间实例相关联的上升沿和下降沿的数据相关时钟信号，以及数模转换器，被配置为接收依赖于数据的时钟信号并产生具有转换的方波输出信号 与产生的数据相关时钟信号相关联的时间。
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3.发明申请公开(公告)号：US20180167056A1
公开(公告)日：2018-06-14
申请号：US15811851
申请日：2016-06-08
Applicant: Intel IP Corporation
Inventor： Thomas Bauernfeind , Andreas Menkhoff , Michael Bruennert
CPC classification number: H03H17/0291 , H03F2200/336 , H03H17/0018 , H03H17/0635
Abstract: An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.
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Patent Agency Ranking
4.发明申请SYSTEM AND METHOD FOR GENERATING A DATA DEPENDENT CLOCK FOR A DAC IN A MODULATOR 有权用于为调制器中的DAC生成数据依赖时钟的系统和方法公开(公告)号：US20150365113A1
公开(公告)日：2015-12-17
申请号：US14303945
申请日：2014-06-13
Applicant: Intel IP Corporation
Inventor： Andreas Menkhoff , Michael Bruennert , Markus Schimper
CPC classification number: H04B1/0475 , H04L27/20 , H04L27/361
Abstract: A modulator and associated method includes a calculation block configured to receive a plurality of digital samples of a modulated baseband signal, and determine time instances associated with predetermined phase crossings of the modulated baseband signal. The modulator further includes a converter circuit configured to generate a data dependent clock signal having rising and falling edges associated with the determined time instances, and a digital to analog converter configured to receive the data dependent clock signal and generate a square wave output signal having transition times associated with the generated data dependent clock signal.
Abstract translation: 调制器和相关联的方法包括被配置为接收调制基带信号的多个数字样本的计算块，并且确定与调制基带信号的预定相位相关联的时间实例。 调制器还包括转换器电路，其被配置为产生具有与所确定的时间实例相关联的上升沿和下降沿的数据相关时钟信号，以及数模转换器，被配置为接收依赖于数据的时钟信号并产生具有转换的方波输出信号 与产生的数据相关时钟信号相关联的时间。
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5.发明授权Circuit, a method and a synthesizer for generating a synthesized signal with a selectable frequency 有权电路，方法和合成器，用于产生具有可选频率的合成信号公开(公告)号：US09281811B2
公开(公告)日：2016-03-08
申请号：US14546127
申请日：2014-11-18
Applicant: Intel IP Corporation
Inventor： Michael Bruennert , Andreas Menkhoff
IPC: H03K5/14
CPC classification number: H03K5/14
Abstract: A circuit for generating a oscillating with a selectable frequency, comprises a delay generator configured to identify a first time instant, the first time instant being delayed with respect to a signal edge of a clock signal oscillating with a predetermined clock frequency. A delay element is configured to provide a signal edge, the signal edge being delayed with respect to the first time instant such that the signal edge is provided at a second time instant corresponding to a signal edge of the synthesized signal.
Abstract translation: 用于产生具有可选频率的振荡的电路包括延迟发生器，其被配置为识别第一时刻，所述第一时刻相对于以预定时钟频率振荡的时钟信号的信号边缘被延迟。 延迟元件被配置为提供信号边缘，信号边缘相对于第一时刻被延迟，使得在对应于合成信号的信号边缘的第二时刻提供信号边缘。
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6.发明申请Circuit, A Method and a Synthesizer for Generating a Synthesized Signal with a Selectable Frequency 有权用于产生具有可选择频率的合成信号的电路，方法和合成器公开(公告)号：US20150171848A1
公开(公告)日：2015-06-18
申请号：US14546127
申请日：2014-11-18
Applicant: Intel IP Corporation
Inventor： Michael Bruennert , Andreas Menkhoff
IPC: H03K5/14
CPC classification number: H03K5/14
Abstract: A circuit for generating a oscillating with a selectable frequency, comprises a delay generator configured to identify a first time instant, the first time instant being delayed with respect to a signal edge of a clock signal oscillating with a predetermined clock frequency. A delay element is configured to provide a signal edge, the signal edge being delayed with respect to the first time instant such that the signal edge is provided at a second time instant corresponding to a signal edge of the synthesized signal.
Abstract translation: 用于产生具有可选频率的振荡的电路包括延迟发生器，其被配置为识别第一时刻，所述第一时刻相对于以预定时钟频率振荡的时钟信号的信号边缘被延迟。 延迟元件被配置为提供信号边缘，信号边缘相对于第一时刻被延迟，使得在对应于合成信号的信号边缘的第二时刻提供信号边缘。
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7.发明申请公开(公告)号：US20200044626A1
公开(公告)日：2020-02-06
申请号：US16543756
申请日：2019-08-19
Applicant: Intel IP Corporation
Inventor： Thomas Bauernfeind , Andreas Menkhoff , Michael Bruennert
Abstract: An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.
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公开(公告)号：US09847676B2
公开(公告)日：2017-12-19
申请号：US14039996
申请日：2013-09-27
Applicant: Intel IP Corporation
Inventor： Paolo Madoglio , Georgios Palaskas , Bernd-Ulrich Klepser , Andreas Menkhoff , Zdravko Boos , Andreas Boehme , Michael Bruennert
CPC classification number: H02J50/20 , H02J7/025 , H02J17/00 , H02J50/90 , H04B1/0475 , H04L27/361 , H04W52/0251 , H04W52/028 , H04W52/52 , Y02D70/00 , Y02D70/40
Abstract: This document discusses apparatus and methods for reducing energy consumption of digital-to-time converter (DTC) based transmitters. In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive phase information from a baseband processor and to provide a first modulation signal for generating a wireless signal, and a detector configured to detect an operating condition of the wireless device and to adjust a parameter of the DTC in response to a change in the operating condition.
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