公开(公告)号：US07589374B2

公开(公告)日：2009-09-15

申请号：US11699990

申请日：2007-01-31

申请人： Jai-Hyuk Song ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee

发明人： Jai-Hyuk Song ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee

IPC分类号： H01L29/788

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11541

摘要： Embodiments of the invention provide a semiconductor device and a related method of fabricating a semiconductor device. In one embodiment, the invention provides a semiconductor device comprising a first gate electrode comprising a lower silicon pattern and an upper silicon pattern and disposed on an active region of a semiconductor substrate, wherein the upper silicon pattern has the same crystal structure as the lower silicon pattern and the active region is defined by a device isolation layer. The semiconductor device further comprises a gate insulating layer disposed between the active region and the first gate electrode.

摘要翻译： 本发明的实施例提供一种制造半导体器件的半导体器件和相关方法。 在一个实施例中，本发明提供一种半导体器件，其包括第一栅电极，其包括下硅图案和上硅图案，并设置在半导体衬底的有源区上，其中上硅图案具有与下硅相同的晶体结构 图案和有源区域由器件隔离层定义。 半导体器件还包括设置在有源区和第一栅电极之间的栅极绝缘层。

公开(公告)号：US07494871B2

公开(公告)日：2009-02-24

申请号：US11647671

申请日：2006-12-29

申请人： Chang-Sub Lee ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song ,  Dong-Yean Oh

发明人： Chang-Sub Lee ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song ,  Dong-Yean Oh

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.

摘要翻译： 半导体存储器件可以包括半导体衬底上的选择晶体管和单元晶体管。 绝缘层覆盖选择晶体管和单元晶体管。 位线在绝缘层中并且电连接到相应的选择晶体管。 沿着相对于半导体衬底具有不同高度的至少两个不同的平行平面布置位线。

公开(公告)号：US07687860B2

公开(公告)日：2010-03-30

申请号：US11425444

申请日：2006-06-21

申请人： Woon-Kyung Lee ,  Jeong-Hyuk Choi ,  Dong-Jun Lee ,  Jai-Hyuk Song

发明人： Woon-Kyung Lee ,  Jeong-Hyuk Choi ,  Dong-Jun Lee ,  Jai-Hyuk Song

IPC分类号： H01L21/8239

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42376 ,  H01L29/66825

摘要： There are provided a memory transistor having a select transistor with asymmetric gate electrode structure and an inverted T-shaped floating gates and a method for forming the same. A gate electrode of the select transistor adjacent to a memory transistor has substantially an inverted T-shaped figure, whereas the gate electrode of the select transistor opposite to the memory transistor has nearly a box-shaped figure. In order to form the floating gate of the memory transistor in shape of the inverted T, a region for the select transistor is closed when opening a region for the memory transistor.

摘要翻译： 提供了一种存储晶体管，其具有具有不对称栅电极结构的选择晶体管和反向T形浮栅及其形成方法。 与存储晶体管相邻的选择晶体管的栅电极具有大致倒T形图形，而与存储晶体管相对的选择晶体管的栅电极具有几乎一个盒形图形。 为了以反相T的形式形成存储晶体管的浮置栅极，当打开存储晶体管的区域时，用于选择晶体管的区域闭合。

公开(公告)号：US07683422B2

公开(公告)日：2010-03-23

申请号：US11464324

申请日：2006-08-14

申请人： Woon-Kyung Lee ,  Jeong-Hyuk Choi ,  Jai-Hyuk Song

发明人： Woon-Kyung Lee ,  Jeong-Hyuk Choi ,  Jai-Hyuk Song

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Non-volatile memory devices include memory cells therein with reduced cell-to-cell coupling capacitance. These memory cells include floating gate electrodes with open-ended wraparound shapes that operate to reduce the cell-to-cell coupling capacitance in a bit line direction, while still maintaining a high coupling ratio between control and floating gate electrodes within each memory cell.

摘要翻译： 非易失性存储器件包括其中具有减小的单元到单元耦合电容的存储单元。 这些存储单元包括具有开口环绕形状的浮动栅极电极，其操作以在位线方向上减小电池到电池耦合电容，同时仍保持每个存储单元内的控制和浮置栅电极之间的高耦合比。

公开(公告)号：US20080081413A1

公开(公告)日：2008-04-03

申请号：US11647671

申请日：2006-12-29

申请人： Chang-Sub Lee ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song ,  Dong-Yean Oh

发明人： Chang-Sub Lee ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song ,  Dong-Yean Oh

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.

摘要翻译： 半导体存储器件可以包括半导体衬底上的选择晶体管和单元晶体管。 绝缘层覆盖选择晶体管和单元晶体管。 位线在绝缘层中并且电连接到相应的选择晶体管。 沿着相对于半导体衬底具有不同高度的至少两个不同的平行平面布置位线。

公开(公告)号：US20070190726A1

公开(公告)日：2007-08-16

申请号：US11699990

申请日：2007-01-31

申请人： Jai-Hyuk Song ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee

发明人： Jai-Hyuk Song ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11541

摘要： Embodiments of the invention provide a semiconductor device and a related method of fabricating a semiconductor device. In one embodiment, the invention provides a semiconductor device comprising a first gate electrode comprising a lower silicon pattern and an upper silicon pattern and disposed on an active region of a semiconductor substrate, wherein the upper silicon pattern has the same crystal structure as the lower silicon pattern and the active region is defined by a device isolation layer. The semiconductor device further comprises a gate insulating layer disposed between the active region and the first gate electrode.

摘要翻译： 本发明的实施例提供一种制造半导体器件的半导体器件和相关方法。 在一个实施例中，本发明提供一种半导体器件，其包括第一栅电极，其包括下硅图案和上硅图案，并设置在半导体衬底的有源区上，其中上硅图案具有与下硅相同的晶体结构 图案和有源区域由器件隔离层定义。 半导体器件还包括设置在有源区和第一栅电极之间的栅极绝缘层。

公开(公告)号：US20070001215A1

公开(公告)日：2007-01-04

申请号：US11480729

申请日：2006-07-03

申请人： Jong-Kwang Llm ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song

发明人： Jong-Kwang Llm ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114

摘要： A nonvolatile memory device includes a device isolating layer disposed at a substrate to define an active region and a floating gate disposed on the active region. The floating gate includes a flat portion and a pair of wall portions. The pair of wall portions extend upward from both edges of the flat portion adjacent to the device isolating layer and face each other. The nonvolatile memory device further includes a tunnel insulating layer interposed between the floating gate and the active region. Moreover, the wall portions and the flat portion are formed of a single layer, and the thickness of the flat portion is larger than a width of the wall portions.

摘要翻译： 非易失性存储器件包括设置在衬底上以限定有源区的器件隔离层和布置在有源区上的浮置栅。 浮动门包括平坦部分和一对壁部分。 所述一对壁部分从邻近所述装置隔离层的所述平坦部分的两个边缘向上延伸并面对彼此。 非易失性存储器件还包括插入在浮置栅极和有源区域之间的隧道绝缘层。 此外，壁部和平坦部由单层形成，平坦部的厚度大于壁部的宽度。

公开(公告)号：US20070090445A1

公开(公告)日：2007-04-26

申请号：US11464324

申请日：2006-08-14

申请人： Woon Lee ,  Jeong-Hyuk Choi ,  Jai-Hyuk Song

发明人： Woon Lee ,  Jeong-Hyuk Choi ,  Jai-Hyuk Song

IPC分类号： H01L29/788 ,  H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Non-volatile memory devices include memory cells therein with reduced cell-to-cell coupling capacitance. These memory cells include floating gate electrodes with open-ended wraparound shapes that operate to reduce the cell-to-cell coupling capacitance in a bit line direction, while still maintaining a high coupling ratio between control and floating gate electrodes within each memory cell.

摘要翻译： 非易失性存储器件包括其中具有减小的单元到单元耦合电容的存储单元。 这些存储单元包括具有开口环绕形状的浮动栅极电极，其操作以在位线方向上减小电池到电池耦合电容，同时仍保持每个存储单元内的控制和浮置栅电极之间的高耦合比。

公开(公告)号：US20080093651A1

公开(公告)日：2008-04-24

申请号：US11700084

申请日：2007-01-31

申请人： Jai-Hyuk Song ,  Jeong-Hyuk Choi ,  Ok-Cheon Hong

发明人： Jai-Hyuk Song ,  Jeong-Hyuk Choi ,  Ok-Cheon Hong

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/66833 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： A flash memory device includes a cell string having a plurality of cell transistors connected in series, and a string selection transistor and a ground selection transistor connected to both ends of the cell string, respectively, wherein the cell transistor has a channel impurity concentration higher than a channel impurity concentration of at least one of the string selection transistor and the ground selection transistor.

摘要翻译： 一种闪速存储器件，包括串联有多个单元晶体管的单元串，以及串联选择晶体管和接地选择晶体管，分别连接到单元串的两端，其中单元晶体管的沟道杂质浓度高于 串选择晶体管和接地选择晶体管中的至少一个的沟道杂质浓度。

公开(公告)号：US07283393B2

公开(公告)日：2007-10-16

申请号：US11483466

申请日：2006-07-10

申请人： Jai-Hyuk Song ,  Jeong-Hyuk Choi

发明人： Jai-Hyuk Song ,  Jeong-Hyuk Choi

IPC分类号： G11C11/34

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A NAND type flash memory device includes a semiconductor substrate, word lines, first and second selection lines, tunnel insulation layers, and selection gate insulation layers. The semiconductor substrate includes a memory transistor region and a selection transistor region. The word lines are arranged in the memory transistor region of the semiconductor substrate, and the selection lines are arranged in the selection transistor region of the semiconductor substrate. The tunnel insulation layers are interposed between the word lines and the semiconductor substrate, and the selection gate insulation layers are interposed between the selection lines and the semiconductor substrate and have a thinner thickness than the thickness of the tunnel insulation layers. Also, the selection gate insulation layers have a thinner thickness in their center region than in their edge portions.