公开(公告)号：US09112045B2

公开(公告)日：2015-08-18

申请号：US13775833

申请日：2013-02-25

申请人： Ju-Hyung Kim ,  Chang-Seok Kang ,  Woon-Kyung Lee

发明人： Ju-Hyung Kim ,  Chang-Seok Kang ,  Woon-Kyung Lee

IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L27/115

CPC分类号： H01L29/792 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/7926

摘要： A nonvolatile memory device comprises a channel pattern, a first interlayer dielectric film and a second interlayer dielectric film spaced apart from each other and stacked over each other, a gate pattern disposed between the first interlayer dielectric film and the second interlayer dielectric film, a trap layer disposed between the gate pattern and the channel pattern and a charge spreading inhibition layer disposed between the channel pattern and the first interlayer dielectric film and between the channel pattern and the second interlayer dielectric film. The charge spreading inhibition layer may include charges inside or on its surface. The charge spreading inhibition layer includes at least one of a metal oxide film or a metal nitride film or a metal oxynitride film having a greater dielectric constant than a silicon oxide film.

摘要翻译： 非易失性存储器件包括彼此间隔开并且彼此堆叠的沟道图案，第一层间电介质膜和第二层间电介质膜，布置在第一层间电介质膜和第二层间电介质膜之间的栅极图案，阱 设置在栅极图案和沟道图案之间的层，以及设置在沟道图案和第一层间电介质膜之间以及沟道图案和第二层间电介质膜之间的电荷扩展抑制层。 电荷扩散抑制层可以包括其表面内部或其表面上的电荷。 电荷扩散抑制层包括金属氧化物膜或金属氮化物膜或具有比氧化硅膜更大的介电常数的金属氧氮化物膜中的至少一种。

公开(公告)号：US20140021527A1

公开(公告)日：2014-01-23

申请号：US13719180

申请日：2012-12-18

申请人： Jung-Min Son ,  Woon-kyung Lee

发明人： Jung-Min Son ,  Woon-kyung Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/788 ,  H01L27/11521

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件可以包括电荷存储结构和栅极。 电荷存储结构形成在基板上。 栅极形成在电荷存储结构上。 栅极包括由硅形成的下部和由金属硅化物形成的上部。 栅极的上部具有大于栅极下部的宽度的宽度。

公开(公告)号：US08470704B2

公开(公告)日：2013-06-25

申请号：US13571502

申请日：2012-08-10

申请人： Seung-Jun Lee ,  Woon-Kyung Lee

发明人： Seung-Jun Lee ,  Woon-Kyung Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile memory device and a method of forming a nonvolatile memory device are provided. The nonvolatile memory device includes an active region of a semiconductor substrate defined by a device isolation layer, a tunnel insulating structure disposed on the active region, and a charge storage structure disposed on the tunnel insulating structure. The nonvolatile memory device also includes a gate interlayer dielectric layer disposed on the charge storage structure, and a control gate electrode disposed on the gate interlayer dielectric layer. The charge storage structure includes an upper charge storage structure and a lower charge storage structure, and the upper charge storage structure has a higher impurity concentration than the lower charge storage structure.

摘要翻译： 提供了非易失性存储器件和形成非易失性存储器件的方法。 非易失性存储器件包括由器件隔离层限定的半导体衬底的有源区，设置在有源区上的隧道绝缘结构，以及设置在隧道绝缘结构上的电荷存储结构。 非易失性存储器件还包括设置在电荷存储结构上的栅极层间介质层和设置在栅极层间介质层上的控制栅电极。 电荷存储结构包括上电荷存储结构和较低电荷存储结构，并且上电荷存储结构具有比下电荷存储结构更高的杂质浓度。

公开(公告)号：US08350344B2

公开(公告)日：2013-01-08

申请号：US13044766

申请日：2011-03-10

申请人： Jung-Min Son ,  Woon-Kyung Lee

发明人： Jung-Min Son ,  Woon-Kyung Lee

IPC分类号： H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L29/788 ,  H01L27/11521

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件可以包括电荷存储结构和栅极。 电荷存储结构形成在基板上。 栅极形成在电荷存储结构上。 栅极包括由硅形成的下部和由金属硅化物形成的上部。 栅极的上部具有大于栅极下部的宽度的宽度。

公开(公告)号：US20120302053A1

公开(公告)日：2012-11-29

申请号：US13571502

申请日：2012-08-10

申请人： SEUNG-JUN LEE ,  WOON-KYUNG LEE

发明人： SEUNG-JUN LEE ,  WOON-KYUNG LEE

IPC分类号： H01L21/283

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile memory device and a method of forming a nonvolatile memory device are provided. The nonvolatile memory device includes an active region of a semiconductor substrate defined by a device isolation layer, a tunnel insulating structure disposed on the active region, and a charge storage structure disposed on the tunnel insulating structure. The nonvolatile memory device also includes a gate interlayer dielectric layer disposed on the charge storage structure, and a control gate electrode disposed on the gate interlayer dielectric layer. The charge storage structure includes an upper charge storage structure and a lower charge storage structure, and the upper charge storage structure has a higher impurity concentration than the lower charge storage structure.

摘要翻译： 提供了非易失性存储器件和形成非易失性存储器件的方法。 非易失性存储器件包括由器件隔离层限定的半导体衬底的有源区，设置在有源区上的隧道绝缘结构，以及设置在隧道绝缘结构上的电荷存储结构。 非易失性存储器件还包括设置在电荷存储结构上的栅极层间介质层和设置在栅极层间介质层上的控制栅电极。 电荷存储结构包括上电荷存储结构和较低电荷存储结构，并且上电荷存储结构具有比下电荷存储结构更高的杂质浓度。

公开(公告)号：US20120238093A1

公开(公告)日：2012-09-20

申请号：US13418585

申请日：2012-03-13

申请人： Sang-yong Park ,  Woon-kyung Lee ,  Jin-taek Park

发明人： Sang-yong Park ,  Woon-kyung Lee ,  Jin-taek Park

IPC分类号： H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/311 ,  H01L21/76838 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of fabricating a semiconductor device includes forming a stacked structure in which 2n (here, n is an integer which is 2 or more) deposited sacrificial layers and 2n deposited insulating layers disposed on the 2n deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2n−1 first recesses penetrating 20 through 2n−1 deposited sacrificial layers and forming a buried insulating layer group including 2n−1 buried insulating layers filling the 2n−1 first recesses respectively. A contact plug group including 2n contact plugs penetrating an uppermost deposited insulating layer of the 2n deposited insulating layers and the 2n−1 buried insulating layers may be formed.

摘要翻译： 一种制造半导体器件的方法包括形成层叠结构，其中分别沉积有牺牲层的2n（n为2以上的整数）和设置在2n个沉积的牺牲层上的2n个沉积的绝缘层交替地沉积在第三 垂直于第一方向和第二方向的方向在具有在彼此垂直的第一和第二方向上延伸的上表面的基板上。 方法包括形成包括通过2n-1个沉积的牺牲层穿透20的2n-1个第一凹部的凹陷组，并且分别形成包括2n-1个第一凹部的2n-1个掩埋绝缘层的掩埋绝缘层组。 可以形成包括穿过2n个沉积绝缘层的最上层的绝缘层和2n-1个绝缘层的2n个接触插塞的接触插塞组。

公开(公告)号：US08053848B2

公开(公告)日：2011-11-08

申请号：US12381380

申请日：2009-03-11

申请人： Jin-Sung Lee ,  Woon-Kyung Lee

发明人： Jin-Sung Lee ,  Woon-Kyung Lee

IPC分类号： H01L29/66

CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573

摘要： A semiconductor device includes a plurality of transistors disposed on a semiconductor substrate, a device isolation layer disposed around the transistors, a guard ring disposed to surround the device isolation layer and the transistors, and a guard region disposed between adjacent transistors.

摘要翻译： 半导体器件包括设置在半导体衬底上的多个晶体管，围绕晶体管设置的器件隔离层，设置成围绕器件隔离层和晶体管的保护环以及设置在相邻晶体管之间的保护区。

公开(公告)号：US08036043B2

公开(公告)日：2011-10-11

申请号：US12480352

申请日：2009-06-08

申请人： Dong-Yean Oh ,  Woon-Kyung Lee

发明人： Dong-Yean Oh ,  Woon-Kyung Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/3454 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11551 ,  H01L27/11556

摘要： A nonvolatile semiconductor memory device including a vertical array structure comprised of bit lines and source lines arranged in the same direction as the bit lines, each source lines corresponding to the bit lines and memory cell strings vertically formed between each pair of the bit lines and source lines. Multiple strings of memory cells can be stacked in the vertical direction, and adjacent memory cell strings may share bit line or source line.

摘要翻译： 一种非易失性半导体存储器件，包括垂直阵列结构，其包括与位线相同方向布置的位线和源极线，每个源极线对应于在每对位线和源极之间垂直形成的位线和存储单元串 线条。 多个存储单元串可以在垂直方向堆叠，并且相邻的存储单元串可以共享位线或源极线。

公开(公告)号：US08035149B2

公开(公告)日：2011-10-11

申请号：US12913865

申请日：2010-10-28

申请人： Woon-Kyung Lee

发明人： Woon-Kyung Lee

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A nonvolatile memory device includes an active region defined by a device isolation layer in a semiconductor substrate, a word line passing over the active region and a charge storage region defined by a crossing of the active region and the word line and disposed between the active region and the word line. The charge storage region is disposed at an oblique angle with respect to the word line.

摘要翻译： 非易失性存储器件包括由半导体衬底中的器件隔离层限定的有源区，通过有源区的字线和由有源区和字线的交叉限定的电荷存储区，并且设置在有源区 和字线。 电荷存储区域相对于字线倾斜设置。

公开(公告)号：US20110220985A1

公开(公告)日：2011-09-15

申请号：US13044766

申请日：2011-03-10

申请人： Jung-Min Son ,  Woon-Kyung Lee

发明人： Jung-Min Son ,  Woon-Kyung Lee

IPC分类号： H01L27/06 ,  H01L29/423 ,  H01L29/788 ,  H01L21/28

CPC分类号： H01L29/788 ,  H01L27/11521

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件可以包括电荷存储结构和栅极。 电荷存储结构形成在基板上。 栅极形成在电荷存储结构上。 栅极包括由硅形成的下部和由金属硅化物形成的上部。 栅极的上部具有大于栅极下部的宽度的宽度。