公开(公告)号：US07589374B2

公开(公告)日：2009-09-15

申请号：US11699990

申请日：2007-01-31

申请人： Jai-Hyuk Song ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee

发明人： Jai-Hyuk Song ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee

IPC分类号： H01L29/788

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11541

摘要： Embodiments of the invention provide a semiconductor device and a related method of fabricating a semiconductor device. In one embodiment, the invention provides a semiconductor device comprising a first gate electrode comprising a lower silicon pattern and an upper silicon pattern and disposed on an active region of a semiconductor substrate, wherein the upper silicon pattern has the same crystal structure as the lower silicon pattern and the active region is defined by a device isolation layer. The semiconductor device further comprises a gate insulating layer disposed between the active region and the first gate electrode.

摘要翻译： 本发明的实施例提供一种制造半导体器件的半导体器件和相关方法。 在一个实施例中，本发明提供一种半导体器件，其包括第一栅电极，其包括下硅图案和上硅图案，并设置在半导体衬底的有源区上，其中上硅图案具有与下硅相同的晶体结构 图案和有源区域由器件隔离层定义。 半导体器件还包括设置在有源区和第一栅电极之间的栅极绝缘层。

公开(公告)号：US07494871B2

公开(公告)日：2009-02-24

申请号：US11647671

申请日：2006-12-29

申请人： Chang-Sub Lee ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song ,  Dong-Yean Oh

发明人： Chang-Sub Lee ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song ,  Dong-Yean Oh

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.

摘要翻译： 半导体存储器件可以包括半导体衬底上的选择晶体管和单元晶体管。 绝缘层覆盖选择晶体管和单元晶体管。 位线在绝缘层中并且电连接到相应的选择晶体管。 沿着相对于半导体衬底具有不同高度的至少两个不同的平行平面布置位线。

公开(公告)号：US20070001215A1

公开(公告)日：2007-01-04

申请号：US11480729

申请日：2006-07-03

申请人： Jong-Kwang Llm ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song

发明人： Jong-Kwang Llm ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114

摘要： A nonvolatile memory device includes a device isolating layer disposed at a substrate to define an active region and a floating gate disposed on the active region. The floating gate includes a flat portion and a pair of wall portions. The pair of wall portions extend upward from both edges of the flat portion adjacent to the device isolating layer and face each other. The nonvolatile memory device further includes a tunnel insulating layer interposed between the floating gate and the active region. Moreover, the wall portions and the flat portion are formed of a single layer, and the thickness of the flat portion is larger than a width of the wall portions.

摘要翻译： 非易失性存储器件包括设置在衬底上以限定有源区的器件隔离层和布置在有源区上的浮置栅。 浮动门包括平坦部分和一对壁部分。 所述一对壁部分从邻近所述装置隔离层的所述平坦部分的两个边缘向上延伸并面对彼此。 非易失性存储器件还包括插入在浮置栅极和有源区域之间的隧道绝缘层。 此外，壁部和平坦部由单层形成，平坦部的厚度大于壁部的宽度。

公开(公告)号：US07687860B2

公开(公告)日：2010-03-30

申请号：US11425444

申请日：2006-06-21

申请人： Woon-Kyung Lee ,  Jeong-Hyuk Choi ,  Dong-Jun Lee ,  Jai-Hyuk Song

发明人： Woon-Kyung Lee ,  Jeong-Hyuk Choi ,  Dong-Jun Lee ,  Jai-Hyuk Song

IPC分类号： H01L21/8239

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42376 ,  H01L29/66825

摘要： There are provided a memory transistor having a select transistor with asymmetric gate electrode structure and an inverted T-shaped floating gates and a method for forming the same. A gate electrode of the select transistor adjacent to a memory transistor has substantially an inverted T-shaped figure, whereas the gate electrode of the select transistor opposite to the memory transistor has nearly a box-shaped figure. In order to form the floating gate of the memory transistor in shape of the inverted T, a region for the select transistor is closed when opening a region for the memory transistor.

摘要翻译： 提供了一种存储晶体管，其具有具有不对称栅电极结构的选择晶体管和反向T形浮栅及其形成方法。 与存储晶体管相邻的选择晶体管的栅电极具有大致倒T形图形，而与存储晶体管相对的选择晶体管的栅电极具有几乎一个盒形图形。 为了以反相T的形式形成存储晶体管的浮置栅极，当打开存储晶体管的区域时，用于选择晶体管的区域闭合。

公开(公告)号：US07683422B2

公开(公告)日：2010-03-23

申请号：US11464324

申请日：2006-08-14

申请人： Woon-Kyung Lee ,  Jeong-Hyuk Choi ,  Jai-Hyuk Song

发明人： Woon-Kyung Lee ,  Jeong-Hyuk Choi ,  Jai-Hyuk Song

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Non-volatile memory devices include memory cells therein with reduced cell-to-cell coupling capacitance. These memory cells include floating gate electrodes with open-ended wraparound shapes that operate to reduce the cell-to-cell coupling capacitance in a bit line direction, while still maintaining a high coupling ratio between control and floating gate electrodes within each memory cell.

摘要翻译： 非易失性存储器件包括其中具有减小的单元到单元耦合电容的存储单元。 这些存储单元包括具有开口环绕形状的浮动栅极电极，其操作以在位线方向上减小电池到电池耦合电容，同时仍保持每个存储单元内的控制和浮置栅电极之间的高耦合比。

公开(公告)号：US20080081413A1

公开(公告)日：2008-04-03

申请号：US11647671

申请日：2006-12-29

申请人： Chang-Sub Lee ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song ,  Dong-Yean Oh

发明人： Chang-Sub Lee ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song ,  Dong-Yean Oh

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.

摘要翻译： 半导体存储器件可以包括半导体衬底上的选择晶体管和单元晶体管。 绝缘层覆盖选择晶体管和单元晶体管。 位线在绝缘层中并且电连接到相应的选择晶体管。 沿着相对于半导体衬底具有不同高度的至少两个不同的平行平面布置位线。

公开(公告)号：US20070190726A1

公开(公告)日：2007-08-16

申请号：US11699990

申请日：2007-01-31

申请人： Jai-Hyuk Song ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee

发明人： Jai-Hyuk Song ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11541

摘要： Embodiments of the invention provide a semiconductor device and a related method of fabricating a semiconductor device. In one embodiment, the invention provides a semiconductor device comprising a first gate electrode comprising a lower silicon pattern and an upper silicon pattern and disposed on an active region of a semiconductor substrate, wherein the upper silicon pattern has the same crystal structure as the lower silicon pattern and the active region is defined by a device isolation layer. The semiconductor device further comprises a gate insulating layer disposed between the active region and the first gate electrode.

摘要翻译： 本发明的实施例提供一种制造半导体器件的半导体器件和相关方法。 在一个实施例中，本发明提供一种半导体器件，其包括第一栅电极，其包括下硅图案和上硅图案，并设置在半导体衬底的有源区上，其中上硅图案具有与下硅相同的晶体结构 图案和有源区域由器件隔离层定义。 半导体器件还包括设置在有源区和第一栅电极之间的栅极绝缘层。

公开(公告)号：US08456918B2

公开(公告)日：2013-06-04

申请号：US12405826

申请日：2009-03-17

申请人： Dong-Yean Oh ,  Woon-Kyung Lee ,  Jai Hyuk Song ,  Chang-Sub Lee

发明人： Dong-Yean Oh ,  Woon-Kyung Lee ,  Jai Hyuk Song ,  Chang-Sub Lee

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection transistor GST. While a programming voltage Vpgm is applied to a selected wordline WL , a cutoff voltage Vss is applied to a nearby unselected wordline closer to the ground selection transistor GST to isolate a first local channel Ch1 from a second local channel Ch2. As the location i of the selected wordline WL increases close to the SST, the second channel potential Vch2 tends to increase excessively, causing errors. The excessive increase of Vch2 is prevented by modifying the voltages applied to string select lines (SSL) and/or to the bit lines (BL), or the pass voltages Vpass applied to the unselected wordlines (WL location i is equal or greater than a predetermined (stored) location number x. If incremental step pulse programming (ISPP) is implemented, the applied voltages are modified only if the ISPP loop count j is equal or greater than a predetermined (stored) critical loop number y.

摘要翻译： 闪速存储器件包括一块NAND单元单元，该块中的每个NAND单元单元包括由多个n个字线控制的n个存储单元晶体管MC，并串联连接在连接到位线的串选择晶体管SST和 接地选择晶体管GST。 当编程电压Vpgm被施加到所选字线WL时，截止电压Vss被施加到靠近接地选择晶体管GST的附近未选字线，以将第一本地信道Ch1与第二本地信道Ch2隔离。 当所选择的字线WL i的位置i增加到接近于SST时，第二通道电位Vch2会过度增加，导致错误。 通过修改施加到串选择线（SSL）和/或位线（BL）的电压或施加到未选择字线（WL ），只有当所选择的字线WL i位置i等于或大于预定（存储的）位置号码x时。 如果实现增量步进脉冲编程（ISPP），只有当ISPP循环计数j等于或大于预定（存储）的关键循环数y时，才施加电压。