-
公开(公告)号：US07494871B2
公开(公告)日：2009-02-24
申请号：US11647671
申请日：2006-12-29
申请人： Chang-Sub Lee , Jeong-Hyuk Choi , Woon-Kyung Lee , Jai-Hyuk Song , Dong-Yean Oh
发明人： Chang-Sub Lee , Jeong-Hyuk Choi , Woon-Kyung Lee , Jai-Hyuk Song , Dong-Yean Oh
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.
摘要翻译： 半导体存储器件可以包括半导体衬底上的选择晶体管和单元晶体管。 绝缘层覆盖选择晶体管和单元晶体管。 位线在绝缘层中并且电连接到相应的选择晶体管。 沿着相对于半导体衬底具有不同高度的至少两个不同的平行平面布置位线。
-
公开(公告)号：US20080081413A1
公开(公告)日：2008-04-03
申请号：US11647671
申请日：2006-12-29
申请人： Chang-Sub Lee , Jeong-Hyuk Choi , Woon-Kyung Lee , Jai-Hyuk Song , Dong-Yean Oh
发明人： Chang-Sub Lee , Jeong-Hyuk Choi , Woon-Kyung Lee , Jai-Hyuk Song , Dong-Yean Oh
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.
摘要翻译： 半导体存储器件可以包括半导体衬底上的选择晶体管和单元晶体管。 绝缘层覆盖选择晶体管和单元晶体管。 位线在绝缘层中并且电连接到相应的选择晶体管。 沿着相对于半导体衬底具有不同高度的至少两个不同的平行平面布置位线。
-
3.发明授权NAND flash memory device and method of operating same to reduce a difference between channel potentials therein 有权NAND闪存器件及其操作方法以减少其中的沟道电位之间的差异公开(公告)号：US08456918B2
公开(公告)日：2013-06-04
申请号：US12405826
申请日：2009-03-17
申请人： Dong-Yean Oh , Woon-Kyung Lee , Jai Hyuk Song , Chang-Sub Lee
发明人： Dong-Yean Oh , Woon-Kyung Lee , Jai Hyuk Song , Chang-Sub Lee
CPC分类号： G11C16/0483 , G11C16/10
摘要： An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection transistor GST. While a programming voltage Vpgm is applied to a selected wordline WL , a cutoff voltage Vss is applied to a nearby unselected wordline closer to the ground selection transistor GST to isolate a first local channel Ch1 from a second local channel Ch2. As the location i of the selected wordline WL increases close to the SST, the second channel potential Vch2 tends to increase excessively, causing errors. The excessive increase of Vch2 is prevented by modifying the voltages applied to string select lines (SSL) and/or to the bit lines (BL), or the pass voltages Vpass applied to the unselected wordlines (WL location i is equal or greater than a predetermined (stored) location number x. If incremental step pulse programming (ISPP) is implemented, the applied voltages are modified only if the ISPP loop count j is equal or greater than a predetermined (stored) critical loop number y.
摘要翻译： 闪速存储器件包括一块NAND单元单元，该块中的每个NAND单元单元包括由多个n个字线控制的n个存储单元晶体管MC，并串联连接在连接到位线的串选择晶体管SST和 接地选择晶体管GST。 当编程电压Vpgm被施加到所选字线WL时，截止电压Vss被施加到靠近接地选择晶体管GST的附近未选字线，以将第一本地信道Ch1与第二本地信道Ch2隔离。 当所选择的字线WL i的位置i增加到接近于SST时，第二通道电位Vch2会过度增加，导致错误。 通过修改施加到串选择线（SSL）和/或位线（BL）的电压或施加到未选择字线（WL ），只有当所选择的字线WL i位置i等于或大于预定（存储的）位置号码x时。 如果实现增量步进脉冲编程（ISPP），只有当ISPP循环计数j等于或大于预定（存储）的关键循环数y时，才施加电压。
-
4.发明申请NON-VOLATILE MEMORY DEVICES INCLUDING DOUBLE DIFFUSED JUNCTION REGIONS AND METHODS OF FABRICATING THE SAME 有权非易失性存储器件，包括双重扩散接点区域及其制造方法公开(公告)号：US20080093648A1
公开(公告)日：2008-04-24
申请号：US11675372
申请日：2007-02-15
申请人： Dong Yean Oh , Jai-Hyuk Song , Chang-Sub Lee , Chang-Hyun Lee , Hyun-Jae Kim
发明人： Dong Yean Oh , Jai-Hyuk Song , Chang-Sub Lee , Chang-Hyun Lee , Hyun-Jae Kim
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/26586 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.
摘要翻译： 非易失性存储器件包括半导体衬底上的串选择栅极和接地选择栅极，以及在串选择栅极和地选择栅极之间的衬底上的多个存储单元栅极。 第一杂质区域延伸到衬底中到多个存储单元门之间的第一深度。 第二杂质区域延伸到衬底中的第二深度，该第二深度大于串选择栅极与紧邻其之间的多个存储单元栅极中的第一深度之间以及在接地选择栅极和最后一个栅极选择栅极之间的第一深度 与其紧邻的多个存储单元门。 还讨论了相关的制造方法。
-
公开(公告)号：US20090257280A1
公开(公告)日：2009-10-15
申请号：US12405826
申请日：2009-03-17
申请人： Dong-Yean Oh , Woo-Kyung Lee , Jai Hyuk Song , Chang-Sub Lee
发明人： Dong-Yean Oh , Woo-Kyung Lee , Jai Hyuk Song , Chang-Sub Lee
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/10
摘要： An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection transistor GST. While a programming voltage Vpgm is applied to a selected wordline WL , a cutoff voltage Vss is applied to a nearby unselected wordline closer to the ground selection transistor GST to isolate a first local channel Ch1 from a second local channel Ch2. As the location i of the selected wordline WL increases close to the SST, the second channel potential Vch2 tends to increase excessively, causing errors. The excessive increase of Vch2 is prevented by modifying the voltages applied to string select lines (SSL) and/or to the bit lines (BL), or the pass voltages Vpass applied to the unselected wordlines (WL location i is equal or greater than a predetermined (stored) location number x. If incremental step pulse programming (ISPP) is implemented, the applied voltages are modified only if the ISPP loop count j is equal or greater than a predetermined (stored) critical loop number y.
摘要翻译： 闪速存储器件包括一块NAND单元单元，该块中的每个NAND单元单元包括由多个n个字线控制的n个存储单元晶体管MC，并串联连接在连接到位线的串选择晶体管SST和 接地选择晶体管GST。 当编程电压Vpgm被施加到所选字线WL时，截止电压Vss被施加到靠近接地选择晶体管GST的附近未选字线，以将第一本地信道Ch1与第二本地信道Ch2隔离。 当所选择的字线WL i的位置i增加到接近于SST时，第二通道电位Vch2会过度增加，导致错误。 通过修改施加到串选择线（SSL）和/或位线（BL）的电压或施加到未选择字线（WL ），只有当所选择的字线WL i位置i等于或大于预定（存储的）位置号码x时。 如果实现增量步进脉冲编程（ISPP），只有当ISPP循环计数j等于或大于预定（存储）的关键循环数y时，才施加电压。
-
6.发明授权公开(公告)号：US07898039B2
公开(公告)日：2011-03-01
申请号：US11675372
申请日：2007-02-15
申请人： Dong-Yean Oh , Jai-Hyuk Song , Chang-Sub Lee , Chang-Hyun Lee , Hyun-Jae Kim
发明人： Dong-Yean Oh , Jai-Hyuk Song , Chang-Sub Lee , Chang-Hyun Lee , Hyun-Jae Kim
CPC分类号： H01L27/11521 , H01L21/26586 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.
摘要翻译： 非易失性存储器件包括半导体衬底上的串选择栅极和接地选择栅极，以及在串选择栅极和地选择栅极之间的衬底上的多个存储单元栅极。 第一杂质区域延伸到衬底中到多个存储单元门之间的第一深度。 第二杂质区域延伸到衬底中的第二深度，该第二深度大于串选择栅极与紧邻其之间的多个存储单元栅极中的第一深度之间以及在接地选择栅极和最后一个栅极选择栅极之间的第一深度 与其紧邻的多个存储单元门。 还讨论了相关的制造方法。
-
7.发明授权Methods of fabricating non-volatile memory devices including double diffused junction regions 有权制造包括双扩散连接区域的非易失性存储器件的方法公开(公告)号：US08324052B2
公开(公告)日：2012-12-04
申请号：US13010583
申请日：2011-01-20
申请人： Dong-Yean Oh , Jai-Hyuk Song , Chang-Sub Lee , Chang-Hyun Lee , Hyun-Jae Kim
发明人： Dong-Yean Oh , Jai-Hyuk Song , Chang-Sub Lee , Chang-Hyun Lee , Hyun-Jae Kim
IPC分类号： H01L21/331
CPC分类号： H01L27/11521 , H01L21/26586 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.
摘要翻译： 非易失性存储器件包括半导体衬底上的串选择栅极和接地选择栅极，以及在串选择栅极和地选择栅极之间的衬底上的多个存储单元栅极。 第一杂质区域延伸到衬底中到多个存储单元门之间的第一深度。 第二杂质区域延伸到衬底中的第二深度，该第二深度大于串选择栅极与紧邻其之间的多个存储单元栅极中的第一深度之间以及在接地选择栅极和最后一个栅极选择栅极之间的第一深度 与其紧邻的多个存储单元门。 还讨论了相关的制造方法。
-
8.发明申请METHODS OF FABRICATING NON-VOLATILE MEMORY DEVICES INCLUDING DOUBLE DIFFUSED JUNCTION REGIONS 有权制造非易失性记忆装置的方法，包括双重扩散结区公开(公告)号：US20110111570A1
公开(公告)日：2011-05-12
申请号：US13010583
申请日：2011-01-20
申请人： Dong-Yean Oh , Jai-Hyuk Song , Chang-Sub Lee , Chang-Hyun Lee , Hyun-Jae Kim
发明人： Dong-Yean Oh , Jai-Hyuk Song , Chang-Sub Lee , Chang-Hyun Lee , Hyun-Jae Kim
IPC分类号： H01L21/8234
CPC分类号： H01L27/11521 , H01L21/26586 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.
摘要翻译： 非易失性存储器件包括半导体衬底上的串选择栅极和接地选择栅极，以及在串选择栅极和地选择栅极之间的衬底上的多个存储单元栅极。 第一杂质区域延伸到衬底中到多个存储单元门之间的第一深度。 第二杂质区域延伸到衬底中的第二深度，该第二深度大于串选择栅极与紧邻其之间的多个存储单元栅极中的第一深度之间以及在接地选择栅极和最后一个栅极选择栅极之间的第一深度 与其紧邻的多个存储单元门。 还讨论了相关的制造方法。
-
9.发明授权Metal oxide semiconductor field effect transistors (MOSFETs) including recessed channel regions and methods of fabricating the same 有权包括凹陷沟道区域的金属氧化物半导体场效应晶体管（MOSFET）及其制造方法公开(公告)号：US07883969B2
公开(公告)日：2011-02-08
申请号：US12106683
申请日：2008-04-21
申请人： Chang-Woo Oh , Dong-Gun Park , Sung-Young Lee , Chang-Sub Lee , Jeong-Dong Choe
发明人： Chang-Woo Oh , Dong-Gun Park , Sung-Young Lee , Chang-Sub Lee , Jeong-Dong Choe
IPC分类号： H01L21/336
CPC分类号： H01L29/66583 , H01L29/1037 , H01L29/66651
摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.
摘要翻译： 提供金属氧化物半导体（MOS）晶体管的单位电池，其在集成电路基板上具有集成电路基板和MOS晶体管。 MOS晶体管包括源极区，漏极区和栅极。 栅极在源极区域和漏极区域之间。 在源区和漏区之间提供沟道区。 沟道区具有比源区和漏区的底表面低的凹陷区域。 还提供了制造晶体管的相关方法。
-
10.发明申请IMAGE SENSOR HAVING 3-DIMENSIONAL TRANSFER TRANSISTOR AND ITS METHOD OF MANUFACTURE 审中-公开具有三维传输晶体管的图像传感器及其制造方法公开(公告)号：US20100207170A1
公开(公告)日：2010-08-19
申请号：US12770957
申请日：2010-04-30
申请人： Kee-Hyun Paik , Jeong-Ho Lyu , Chang-Sub Lee , Keun-Ho Lee
发明人： Kee-Hyun Paik , Jeong-Ho Lyu , Chang-Sub Lee , Keun-Ho Lee
IPC分类号： H01L31/112
CPC分类号： H01L27/14603 , H01L27/14689
摘要： In an embodiment, an image sensor includes an isolation layer disposed in a semiconductor substrate to define a first active region and a second active region extending from the first active region. A photodiode is disposed in a portion of the first active region. A floating diffusion region is provided in the second active region at a position spaced apart from the photodiode. A transfer gate electrode is disposed on the second active region between the photodiode and the floating diffusion region. The transfer gate electrode is disposed to cover both sidewalls and an upper portion of the second active region. The transfer gate electrode has a region extending onto the first active region and overlapping the photodiode. The photodiode has a protrusion into the second active region at the portion adjacent to the transfer gate electrode. A deep n-impurity region of the photodiode extends in the protrusion.
摘要翻译： 在一个实施例中，图像传感器包括设置在半导体衬底中以限定第一有源区和从第一有源区延伸的第二有源区的隔离层。 光电二极管设置在第一有源区的一部分中。 浮动扩散区设置在与光电二极管间隔开的位置处的第二有源区中。 传输栅电极设置在光电二极管和浮动扩散区之间的第二有源区上。 转移栅电极设置成覆盖第二有源区的两个侧壁和上部。 传输栅电极具有延伸到第一有源区上并与光电二极管重叠的区域。 光电二极管在与传输栅电极相邻的部分具有到第二有源区的突起。 光电二极管的深n杂质区域在突起中延伸。
-
-
-
-
-
-
-
-
-
搜索结果
49 条记录 (耗时 0.031 秒)
