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公开(公告)号：US12148842B2
公开(公告)日：2024-11-19
申请号：US18181572
申请日：2023-03-10
Applicant: Japan Display Inc.
Inventor： Masataka Ikeda , Hirotaka Hayashi , Hitoshi Tanaka
IPC: H01L29/786 , G02F1/167 , G02F1/16766 , H01L27/12 , H01L49/02
Abstract: According to one embodiment, a semiconductor substrate includes a first basement, a gate line, a source line, an insulating film, a first pixel electrode, and a first transistor and a second transistor connected parallel at positions between the source line and the first pixel electrode. Each of a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor includes a first region, a second region, and a channel region. The first semiconductor layer and the second semiconductor layer are in contact with a first surface that is a surface of the insulating film on the source line side. The channel region of each of the first semiconductor layer and the second semiconductor layer wholly overlaps the gate line.
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公开(公告)号：US12249676B2
公开(公告)日：2025-03-11
申请号：US17316927
申请日：2021-05-11
Applicant: Japan Display Inc.
Inventor： Osamu Itou , Masanobu Ikeda , Masataka Ikeda
Abstract: A display device includes a substrate, a plurality of pixels, a light emitting element, and an inorganic insulating layer. The pixels are provided to the substrate. The light emitting element is provided to each of the pixels. The inorganic insulating layer has translucency and covers at least part of the light emitting element. The inorganic insulating layer includes a side part and an extending part. The side part is provided to the side surface of the light emitting element. The extending part is provided at a side on the lower end of the side part and extending toward the outer side of the light emitting element than the side part in planar view seen from the normal direction of the substrate.
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公开(公告)号：US11194206B2
公开(公告)日：2021-12-07
申请号：US17203771
申请日：2021-03-17
Applicant: Japan Display Inc.
Inventor： Gen Koide , Masataka Ikeda
IPC: G02F1/1333 , G02F1/1362 , H01L27/12
Abstract: According to one embodiment, a semiconductor substrate includes a signal line including a first area overlapping a first concave groove portion and a second area not overlapping the first concave groove portion. The signal line includes a first layer and a second layer. A first end portion of the first layer of the first area projects from a side surface of the second layer in a direction parallel to a plane of the first base. The first layer of the first area includes a first portion between the side surface of the second layer and the first end portion. The first portion is in contact with a side surface of the first concave groove portion, and the side surface of the second layer is covered with the first portion in the first concave groove portion.
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公开(公告)号：US12158677B2
公开(公告)日：2024-12-03
申请号：US18426348
申请日：2024-01-30
Applicant: Japan Display Inc.
Inventor： Masataka Ikeda
IPC: G02F1/1362 , G02F1/1343 , G02F1/1368 , H01L27/12
Abstract: A display device includes a first conductive layer having a first region extending in a first direction and a second region intersecting the first region on a first substrate, a first insulating film arranged on the first conductive layer, an oxide semiconductor layer arranged along the second region on the first insulating film, a second conductive layer and a third conductive layer connected to the oxide semiconductor layer and arranged along the second region, a second insulating film arranged on the third conductive layer, and a pixel electrode arranged on the second insulating film, wherein the third conductive layer has a third region along the first direction and a fourth region along the second region, and the pixel electrode is connected to the third conductive layer in the third region via an opening in the second insulating film.
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公开(公告)号：US12092930B2
公开(公告)日：2024-09-17
申请号：US18505329
申请日：2023-11-09
Applicant: Japan Display Inc.
Inventor： Masataka Ikeda
IPC: G02F1/1343 , G02F1/1334
CPC classification number: G02F1/134336 , G02F1/1334 , G02F1/134318
Abstract: A display device includes a pixel electrode layer in which a plurality of pixel electrodes is arranged in a first direction and a second direction crossing the first direction, a first substrate including a first surface and a second surface on which the pixel electrode layer is arranged, a second substrate including a third surface arranged to face the second surface, a common electrode layer arranged on the third surface, and a liquid crystal layer arranged between the common electrode layer and the pixel electrode layer. Each of the plurality of pixel electrodes includes a plurality of first openings.
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Patent Agency Ranking
公开(公告)号：US12219075B2
公开(公告)日：2025-02-04
申请号：US18115796
申请日：2023-03-01
Applicant: Japan Display Inc.
Inventor： Masataka Ikeda
Abstract: A detection device includes a pixel including a photodiode connected to a gate electrode of a first transistor, and a control circuit configured to control an operation of the pixel in a reset period (including a first and a second periods) for resetting the gate electrode, an exposure period for exposing the photo diode, and a read-out period (a fourth period) to read out a voltage associated with the exposure of the photodiode. The control circuit is configured to read out a first voltage during the first period, read out a second voltage during the second period after stopping a supply of a reset voltage to the gate electrode, read out a third voltage in the fourth period after the exposure period, output a difference value between the first and the second voltages as PUF-ID data and a difference value between the third and the second voltages as detection data.
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公开(公告)号：US12158679B2
公开(公告)日：2024-12-03
申请号：US18312608
申请日：2023-05-05
Applicant: Japan Display Inc.
Inventor： Kentaro Kawai , Masataka Ikeda , Hirotaka Hayashi , Yuuji Oomori , Yoshihide Ohue
IPC: G02F1/1362 , G02F1/1345 , G02F1/1368 , G02F1/1334 , G09G3/36 , H01L27/12
Abstract: A display device includes a first pixel, a second pixel, and a third pixel arranged in a first direction in a display area arranged on a first substrate, a first source wiring, a second wiring, and a third wiring extending in the first direction, and connected to each of the first pixel to the third pixel, and a first gate wiring, a second gate wiring, and a third wiring intersecting the first direction, and connected to each of the first pixel to the third pixel. The first pixel includes a first transistor electrically connected to the first gate wiring and the first source wiring and a liquid crystal element electrically connected to the first transistor, the first pixel to the third pixel are arranged between the first source wiring and the third source wiring, and the second source wiring, and the first source wiring intersects the third source wiring.
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公开(公告)号：US12025891B1
公开(公告)日：2024-07-02
申请号：US18402788
申请日：2024-01-03
Applicant: Japan Display Inc.
Inventor： Masataka Ikeda
IPC: G02F1/1362 , G02F1/1333 , G02F1/1334 , G02F1/1343 , G02F1/1368 , H01L27/12
CPC classification number: G02F1/136227 , G02F1/1334 , G02F1/1368 , H01L27/1248
Abstract: A display device includes a transistor having an oxide semiconductor layer, a gate electrode opposed to the semiconductor layer, and a gate insulating film arranged between the oxide semiconductor layer and the gate electrode, a drain electrode connected to the transistor, a pixel electrode connected to the drain electrode, and a first insulating film and a second insulating film arranged between the drain electrode and the pixel electrode.
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公开(公告)号：US11694454B2
公开(公告)日：2023-07-04
申请号：US17448386
申请日：2021-09-22
Applicant: Japan Display Inc.
Inventor： Masataka Ikeda
CPC classification number: G06V20/80 , G06F3/044 , G06F3/04166 , H04L9/3278 , G06V20/95
Abstract: An information processing device comprises an electronic device, an averaging circuit acquiring output signals from the electronic device multiple times in a predetermined period and averaging the signals acquired multiple times, a memory circuit storing an averaged signal averaged by the averaging circuit and a PUF-ID extraction circuit generating a unique identifier based on the averaged signal.
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公开(公告)号：US11682732B2
公开(公告)日：2023-06-20
申请号：US17184708
申请日：2021-02-25
Applicant: Japan Display Inc.
Inventor： Hirotaka Hayashi , Masataka Ikeda
IPC: H01L29/786 , G02F1/167
CPC classification number: H01L29/7869 , G02F1/167
Abstract: According to one embodiment, a semiconductor layer includes a base, a scanning line disposed over the base, a signal line disposed over the base, a transistor overlapping the scanning line and the signal line and including a first oxide semiconductor layer connected to the signal line, and second oxide semiconductor layers disposed in a same layer as the first oxide semiconductor layer. The second oxide semiconductor layers are disposed around the transistor, and the second oxide semiconductor layers are floating.
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