公开(公告)号：US12191316B2

公开(公告)日：2025-01-07

申请号：US18439855

申请日：2024-02-13

Applicant: Japan Display Inc.

Inventor： Tatsuya Toda ,  Toshinari Sasaki ,  Masayoshi Fuchi

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/3225 ,  G09G3/3266 ,  H10K59/12 ,  H10K59/123 ,  H10K59/124 ,  H10K59/131

Abstract: A semiconductor device including: a first gate electrode; a first gate insulating layer on the first gate electrode; a first oxide semiconductor layer on the first insulating layer; source and drain electrodes connected to the first oxide semiconductor layer; a second gate insulating layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the second gate insulating layer; a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer; a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping with the second oxide semiconductor layer in a planar view; and a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture.

公开(公告)号：US12094980B2

公开(公告)日：2024-09-17

申请号：US17483836

申请日：2021-09-24

Applicant: Japan Display Inc.

Inventor： Tatsuya Toda ,  Masashi Tsubuku ,  Toshinari Sasaki

IPC: H01L27/12 ,  G01N23/20091 ,  H01L29/786

CPC classification number: H01L29/7869 ,  G01N23/20091 ,  H01L27/1225 ,  H01J2237/2442

Abstract: A semiconductor device includes an oxide semiconductor layer including indium, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, and a first electrode arranged above the oxide semiconductor layer and being in contact with the oxide semiconductor layer from above the oxide semiconductor layer. The indium is unevenly distributed in an unevenly distributed region among the oxide semiconductor layer. The unevenly distributed region overlaps with the first conductive layer in a planar view.

公开(公告)号：US11594641B2

公开(公告)日：2023-02-28

申请号：US17111810

申请日：2020-12-04

Applicant: Japan Display Inc.

Inventor： Masashi Tsubuku ,  Michiaki Sakamoto ,  Takashi Okada ,  Toshiki Kaneko ,  Tatsuya Toda

IPC: H01L29/00 ,  H01L29/786 ,  H01L29/417

Abstract: A semiconductor device includes a gate electrode on a substrate, a gate insulating film on the gate electrode, an oxide semiconductor film via the gate insulating film on the gate electrode, a source electrode and a drain electrode on the oxide semiconductor film, a protective film provided on the source electrode and the drain electrode; and a conductive layer provided on the protective film and overlapped on the oxide semiconductor layer. The protective film includes a first silicon oxide film and a first silicon nitride film. The first oxide film is in contact with the oxide semiconductor layer. The gate insulating film includes a second silicon nitride film and a second silicon oxide film. The second silicon oxide film is in contact with the oxide semiconductor layer. The oxide semiconductor layer has a first region located between the source electrode and the drain electrode in a plan view.

公开(公告)号：US10964724B2

公开(公告)日：2021-03-30

申请号：US16109175

申请日：2018-08-22

Applicant: Japan Display Inc.

Inventor： Tatsuya Toda

IPC: H01L27/12 ,  G09G3/36 ,  G09G3/3266 ,  G09G3/3233 ,  H01L23/532 ,  H01L27/32 ,  G02F1/1368 ,  G02F1/133 ,  G02F1/1335 ,  H01L29/786 ,  H01L29/423 ,  H01L29/417

Abstract: The purpose of the present invention is to avoid an inflection point in Vg-Id characteristics of the Thin Film transistor, and to avoid step disconnection of the insulating film formed on the semiconductor layer in the display device. The concrete structure of the present invention is: a display device including a TFT substrate having a thin film transistor (TFT) comprising; the TFT having a channel width and a channel length, a gate insulating film formed on a gate electrode, a semiconductor layer formed on the gate insulating film, wherein the gate electrode, near its edge, has a first sloping surface having a first taper angle in a cross sectional view along the direction of the channel width, an edge of the semiconductor layer in the cross sectional view along the direction of the channel width lies on the first sloping surface of the gate electrode.

公开(公告)号：US11935898B2

公开(公告)日：2024-03-19

申请号：US17031999

申请日：2020-09-25

Applicant: Japan Display Inc.

Inventor： Tatsuya Toda ,  Toshinari Sasaki ,  Masayoshi Fuchi

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/3225 ,  G09G3/3266 ,  H10K59/12 ,  H10K59/123 ,  H10K59/124 ,  H10K59/131

CPC classification number: H01L27/124 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G09G3/3225 ,  G09G3/3266 ,  H01L27/1259 ,  H10K59/123 ,  H10K59/124 ,  H10K59/131 ,  G02F1/136295 ,  G09G2300/0861 ,  H01L27/1225 ,  H01L27/1255 ,  H10K59/1201

Abstract: A semiconductor device including: a first gate electrode; a first gate insulating layer on the first gate electrode; a first oxide semiconductor layer on the first insulating layer; source and drain electrodes connected to the first oxide semiconductor layer; a second gate insulating layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the second gate insulating layer; a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer; a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping with the second oxide semiconductor layer in a planar view; and a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture.

公开(公告)号：US11927859B2

公开(公告)日：2024-03-12

申请号：US17447740

申请日：2021-09-15

Applicant: Japan Display Inc.

Inventor： Masashi Tsubuku ,  Takeshi Sakai ,  Tatsuya Toda

IPC: G02F1/1368 ,  H10K59/124 ,  H10K71/00 ,  H10K59/12

CPC classification number: G02F1/1368 ,  H10K59/124 ,  H10K71/00 ,  H10K59/1201

Abstract: A display device comprising a transistor and a display element over the transistor, wherein the transistor includes a gate electrode on an insulating surface, a gate insulating layer on the gate electrode, and source/drain electrodes on the oxide semiconductor layer and the gate insulating layer, each including a first conductive layer containing nitrogen and a second conductive layer on the first conductive layer, and an insulating layer contains oxygen on the oxide semiconductor layer and the source/drain electrodes.

公开(公告)号：US11342463B2

公开(公告)日：2022-05-24

申请号：US17036298

申请日：2020-09-29

Applicant: Japan Display Inc.

Inventor： Tatsuya Toda ,  Masashi Tsubuku

IPC: H01L29/786 ,  H01L21/473

Abstract: A semiconductor device comprising: an oxide semiconductor layer including indium; a gate electrode facing to the oxide semiconductor layer; a gate insulating layer between the oxide semiconductor layer and the gate electrode; a first conductive layer arranged above the oxide semiconductor layer and being in contact with the oxide semiconductor layer from above the oxide semiconductor layer; an oxide portion formed on the oxide semiconductor layer and at an edge of the first conductive layer, the oxide portion being a oxide of the first conductive layer.

公开(公告)号：US12119407B2

公开(公告)日：2024-10-15

申请号：US18163045

申请日：2023-02-01

Applicant: Japan Display Inc.

Inventor： Masashi Tsubuku ,  Michiaki Sakamoto ,  Takashi Okada ,  Toshiki Kaneko ,  Tatsuya Toda

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/41733

Abstract: A semiconductor device includes a gate electrode on a substrate, a gate insulating film on the gate electrode, an oxide semiconductor film via the gate insulating film on the gate electrode, a source electrode and a drain electrode on the oxide semiconductor film, a protective film provided on the source electrode and the drain electrode; and a conductive layer provided on the protective film and overlapped on the oxide semiconductor layer. The protective film includes a first silicon oxide film and a first silicon nitride film. The first oxide film is in contact with the oxide semiconductor layer. The gate insulating film includes a second silicon nitride film and a second silicon oxide film. The second silicon oxide film is in contact with the oxide semiconductor layer. The oxide semiconductor layer has a first region located between the source electrode and the drain electrode in a plan view.

公开(公告)号：US12010871B2

公开(公告)日：2024-06-11

申请号：US17199991

申请日：2021-03-12

Applicant: Japan Display Inc.

Inventor： Masashi Tsubuku ,  Tatsuya Toda

IPC: H10K59/121 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H10K59/1213 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78648 ,  H01L29/7869 ,  H01L27/1225 ,  H01L2029/42388

Abstract: A thin film transistor including: an active layer formed of an oxide semiconductor including at least indium and gallium; a gate electrode; a first gate insulating layer disposed between the active layer and the gate electrode on the gate electrode side; and a second gate insulating layer, which is a hydrogen block layer, disposed between the active layer and the gate electrode on the active layer side.