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    Buffer with inductance-based capacitive-load reduction
    1.
    发明授权
    Buffer with inductance-based capacitive-load reduction 失效
    具有基于电感的电容负载减小的缓冲器

    公开(公告)号：US07728629B2

    公开(公告)日：2010-06-01

    申请号：US11526306

    申请日：2006-09-25

    申请人： Jinghong Chen

    发明人： Jinghong Chen

    IPC分类号： H03K19/094

    CPC分类号： H03F3/301 ,  H03F2203/30099 ,  H03F2203/30132

    摘要： A buffer circuit uses (e.g., active) inductors for driving capacitive loads. In one embodiment, the buffer circuit has one or more stages, each stage having one CMOS inverter. Each CMOS inverter has one NMOS transistor and one PMOS transistor and is coupled to a stage input and a stage output. Additionally, at least one stage of the buffer circuit has two inductors, each coupled between a different voltage reference for the buffer circuit and the stage output. One inductor has a PMOS transistor coupled to the gate of an NMOS transistor and the other inductor has an NMOS transistor coupled to the gate of a PMOS transistor. When driving capacitive loads, the inductors partially tune out the apparent load capacitance CL, thereby improving the charging capabilities of inverter and enabling quicker charge and discharge times. Furthermore, partially tuning out apparent load capacitance facilitates the driving of larger capacitive loads.

    摘要翻译： 缓冲电路使用（例如，有源）电感器来驱动电容性负载。 在一个实施例中，缓冲电路具有一个或多个级，每级具有一个CMOS反相器。 每个CMOS反相器具有一个NMOS晶体管和一个PMOS晶体管，并且耦合到级输入和级输出。 此外，缓冲电路的至少一级具有两个电感器，每个电感耦合在用于缓冲电路的不同参考电压和级输出之间。 一个电感器具有耦合到NMOS晶体管的栅极的PMOS晶体管，另一个电感器具有耦合到PMOS晶体管的栅极的NMOS晶体管。 当驱动容性负载时，电感器部分地调出视在负载电容CL，从而提高逆变器的充电能力，并且能够实现更快的充电和放电时间。 此外，部分调谐视在负载电容有助于驱动较大的容性负载。

    Techniques for designing wide band low noise amplifiers
    2.
    发明授权
    Techniques for designing wide band low noise amplifiers 有权
    技术用于设计宽带低噪声放大器

    公开(公告)号：US07639079B2

    公开(公告)日：2009-12-29

    申请号：US11673264

    申请日：2007-02-09

    申请人： Tienyu Chang ,  Jinghong Chen

    发明人： Tienyu Chang ,  Jinghong Chen

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45188 ,  H03F1/08 ,  H03F1/26 ,  H03F1/42 ,  H03F3/45179 ,  H03F2200/294 ,  H03F2200/36 ,  H03F2200/372 ,  H03F2203/45481 ,  H03F2203/45526 ,  H03F2203/45532 ,  H03F2203/45554

    摘要： A wideband amplifier having an amplifier input terminal and an amplifier output terminal includes at least one transistor coupled to the amplifier input terminal and an impedance element coupled between the amplifier input terminal and the amplifier output terminal. A feedback signal is transmitted between the amplifier output terminal and the amplifier input terminal by way of the impedance element wherein the feedback signal varies in accordance with changes in an impedance of the impedance element so as to peak a frequency response of the amplifier.

    摘要翻译： 具有放大器输入端子和放大器输出端子的宽带放大器包括耦合到放大器输入端子的至少一个晶体管和耦合在放大器输入端子和放大器输出端子之间的阻抗元件。 反馈信号通过阻抗元件在放大器输出端和放大器输入端之间传输，其中反馈信号根据阻抗元件的阻抗变化而变化，从而使放大器的频率响应达到峰值。

    Multi-gain amplifier with input impedance control
    7.
    发明授权
    Multi-gain amplifier with input impedance control 失效
    具有输入阻抗控制的多增益放大器

    公开(公告)号：US07382189B2

    公开(公告)日：2008-06-03

    申请号：US11526855

    申请日：2006-09-25

    申请人： Jinghong Chen ,  Shaorui Li ,  Lawrence A. Rigge

    发明人： Jinghong Chen ,  Shaorui Li ,  Lawrence A. Rigge

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45188 ,  H03F1/56 ,  H03F3/19 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/45316 ,  H03F2203/45332 ,  H03F2203/45506 ,  H03F2203/45616 ,  H03F2203/45704 ,  H03F2203/45726 ,  H03H7/38

    摘要： In one embodiment, an amplifier circuit has at least one branch and current-source circuitry providing a tail current to the branch, which has at least one load tank, at least one input transistor coupled to the load tank, and variable-impedance circuitry coupled between an input node of the amplifier circuit and the gate of the input transistor. The transconductance of the input transistor can be altered to achieve two or more different gain settings for the amplifier circuit. The variable-impedance circuitry can be controlled to contribute any one of at least two different levels of impedance to the overall input impedance of the amplifier circuit. If the transconductance of the input transistor is reduced, then the variable-impedance circuitry can increase the level of impedance contributed to the overall input impedance of the amplifier circuit such that the overall input impedance of the amplifier circuit remains substantially unchanged.

    摘要翻译： 在一个实施例中，放大器电路具有至少一个分支和电流源电路，其向分支提供尾电流，该分支具有至少一个负载箱，耦合到负载箱的至少一个输入晶体管和耦合到可变阻抗电路 在放大器电路的输入节点和输入晶体管的栅极之间。 可以改变输入晶体管的跨导以实现放大器电路的两个或多个不同的增益设置。 可控制可变阻抗电路可以对放大器电路的整个输入阻抗提供至少两个不同等级的阻抗中的任何一个。 如果输入晶体管的跨导减小，则可变阻抗电路可以增加对放大器电路的总体输入阻抗贡献的阻抗水平，使得放大器电路的总体输入阻抗基本上保持不变。

    Quadrature LC voltage controlled oscillator with opposed bias and coupling control stages
    8.
    发明授权
    Quadrature LC voltage controlled oscillator with opposed bias and coupling control stages 失效
    具有相对偏置和耦合控制级的正交LC压控振荡器

    公开(公告)号：US07342462B1

    公开(公告)日：2008-03-11

    申请号：US11462180

    申请日：2006-08-03

    申请人： Jinghong Chen

    发明人： Jinghong Chen

    IPC分类号： H03B5/12 ,  H03B27/00 ,  H03L7/24

    CPC分类号： H03L7/00 ,  H03B27/00 ,  H03L7/099

    摘要： A voltage controlled oscillator unit is provided with cross coupled voltage controlled oscillators to generate quadrature phases. One control stage adjusts coupling between the oscillators. Another control stage adjusts the tail current that applies operating bias to the oscillators and to the couplers, respectively. The cross coupling and tail current control stages are arranged so that tuning one simultaneously and oppositely tunes the other for simultaneous adjustment in opposite directions. This limits the power consumption of the oscillator unit throughout the range of frequency control.

    摘要翻译： 压控振荡器单元设有交叉耦合电压控制振荡器以产生正交相位。 一个控制级调节振荡器之间的耦合。 另一个控制级分别调节向振荡器和耦合器施加工作偏压的尾电流。 交叉耦合和尾电流控制级被布置成使得调谐一个同时并相反地调谐另一个以在相反方向上同时进行调整。 这限制了整个频率控制范围内振荡器单元的功耗。

    TECHNIQUES FOR DESIGNING WIDE BAND LOW NOISE AMPLIFIERS
    9.
    发明申请
    TECHNIQUES FOR DESIGNING WIDE BAND LOW NOISE AMPLIFIERS 有权
    设计宽带低噪声放大器的技术

    公开(公告)号：US20070120603A1

    公开(公告)日：2007-05-31

    申请号：US11673264

    申请日：2007-02-09

    申请人： Tienyu Chang ,  Jinghong Chen

    发明人： Tienyu Chang ,  Jinghong Chen

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45188 ,  H03F1/08 ,  H03F1/26 ,  H03F1/42 ,  H03F3/45179 ,  H03F2200/294 ,  H03F2200/36 ,  H03F2200/372 ,  H03F2203/45481 ,  H03F2203/45526 ,  H03F2203/45532 ,  H03F2203/45554

    摘要： A wideband amplifier having an amplifier input terminal and an amplifier output terminal includes at least one transistor coupled to the amplifier input terminal and an impedance element coupled between the amplifier input terminal and the amplifier output terminal. A feedback signal is transmitted between the amplifier output terminal and the amplifier input terminal by way of the impedance element wherein the feedback signal varies in accordance with changes in an impedance of the impedance element so as to peak a frequency response of the amplifier.

    摘要翻译： 具有放大器输入端子和放大器输出端子的宽带放大器包括耦合到放大器输入端子的至少一个晶体管和耦合在放大器输入端子和放大器输出端子之间的阻抗元件。 反馈信号通过阻抗元件在放大器输出端和放大器输入端之间传输，其中反馈信号根据阻抗元件的阻抗变化而变化，从而使放大器的频率响应达到峰值。

    CML circuit devices having improved headroom
    10.
    发明授权
    CML circuit devices having improved headroom 失效
    CML电路器件具有改善的净空

    公开(公告)号：US07388406B2

    公开(公告)日：2008-06-17

    申请号：US11420098

    申请日：2006-05-24

    申请人： Jinghong Chen

    发明人： Jinghong Chen

    IPC分类号： H03K19/20 ,  H03K19/094

    CPC分类号： H03K19/09432

    摘要： A CML digital circuit includes a load coupled between a power supply node and at least one output node and a logic circuit component coupled to the output node. The logic circuit component has at least one data input node. The logic circuit component comprises a first circuit module and a second circuit module. A first tail current source is coupled to the first circuit module. A second tail current source is coupled to the second circuit module. A first switch is coupled between the power supply node and the first tail current source. A second switch is coupled between the power supply node and the second tail current source, wherein the first switch is triggered to deactivate the first circuit module when the second circuit module is operating and the second switch is triggered to deactivate the second circuit module when the first circuit module is operating.

    摘要翻译： CML数字电路包括耦合在电源节点和至少一个输出节点之间的负载以及耦合到输出节点的逻辑电路组件。 逻辑电路组件具有至少一个数据输入节点。 逻辑电路部件包括第一电路模块和第二电路模块。 第一尾电流源耦合到第一电路模块。 第二尾电流源耦合到第二电路模块。 第一开关耦合在电源节点和第一尾电流源之间。 第二开关耦合在电源节点和第二尾电流源之间，其中第一开关被触发以在第二电路模块工作时停用第一电路模块，并且当第二开关被触发时停用第二电路模块 第一个电路模块正在运行。