利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

42 条记录 (耗时 0.017 秒)

    Amplifier design with biasing and power control aspects
    1.
    发明授权
    Amplifier design with biasing and power control aspects 有权
    具有偏置和功率控制方面的放大器设计

    公开(公告)号：US07920027B2

    公开(公告)日：2011-04-05

    申请号：US12098936

    申请日：2008-04-07

    申请人： Arvind Keerti

    发明人： Arvind Keerti

    IPC分类号： H03F3/18

    CPC分类号： H03F3/3022 ,  H03F1/0261 ,  H03F1/0277 ,  H03F1/301 ,  H03F1/308 ,  H03F1/3205 ,  H03F3/72 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2203/30015 ,  H03F2203/30099 ,  H03F2203/30132 ,  H03F2203/7236 ,  H03G1/0088

    摘要： Techniques for biasing an amplifier using a replica circuit are disclosed. In an embodiment, a replica circuit having substantially the same topology and sizing as a push-pull amplifier circuit is coupled to a main push-pull amplifier circuit. A transistor in the replica circuit may be biased using feedback to generate a predetermined DC output voltage level, and such bias level may be applied to a corresponding transistor in the main push-pull amplifier circuit. In another embodiment, a transistor in a current bias module may be used to bias corresponding transistors in the main push-pull amplifier circuit and the replica circuit. Further techniques are disclosed for configuring the amplifier to have a non-uniform step size with finer resolution at lower power levels and coarser resolution at higher power levels to reduce power consumption at lower power levels.

    摘要翻译： 公开了使用复制电路偏置放大器的技术。 在一个实施例中，具有与推挽放大器电路基本相同的拓扑和尺寸的复制电路耦合到主推挽放大器电路。 可以使用反馈来偏置复制电路中的晶体管以产生预定的DC输出电压电平，并且可以将这种偏置电平施加到主推挽放大器电路中的相应晶体管。 在另一个实施例中，电流偏置模块中的晶体管可用于偏置主推挽放大器电路和复制电路中的相应晶体管。 公开了用于将放大器配置为具有在较低功率水平下具有更精细分辨率的非均匀步长以及在较高功率水平下较粗分辨率以降低较低功率水平下的功率消耗的技术。

    AMPLIFIER DESIGN WITH BIASING AND POWER CONTROL ASPECTS
    2.
    发明申请
    AMPLIFIER DESIGN WITH BIASING AND POWER CONTROL ASPECTS 有权
    具有偏置和功率控制方面的放大器设计

    公开(公告)号：US20090251217A1

    公开(公告)日：2009-10-08

    申请号：US12098936

    申请日：2008-04-07

    申请人： Arvind Keerti

    发明人： Arvind Keerti

    IPC分类号： H03F3/18 ,  H03F3/26

    CPC分类号： H03F3/3022 ,  H03F1/0261 ,  H03F1/0277 ,  H03F1/301 ,  H03F1/308 ,  H03F1/3205 ,  H03F3/72 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2203/30015 ,  H03F2203/30099 ,  H03F2203/30132 ,  H03F2203/7236 ,  H03G1/0088

    摘要： Techniques for biasing an amplifier using a replica circuit are disclosed. In an embodiment, a replica circuit having substantially the same topology and sizing as a push-pull amplifier circuit is coupled to a main push-pull amplifier circuit. A transistor in the replica circuit may be biased using feedback to generate a predetermined DC output voltage level, and such bias level may be applied to a corresponding transistor in the main push-pull amplifier circuit. In another embodiment, a transistor in a current bias module may be used to bias corresponding transistors in the main push-pull amplifier circuit and the replica circuit. Further techniques are disclosed for configuring the amplifier to have a non-uniform step size with finer resolution at lower power levels and coarser resolution at higher power levels to reduce power consumption at lower power levels.

    摘要翻译： 公开了使用复制电路偏置放大器的技术。 在一个实施例中，具有与推挽放大器电路基本相同的拓扑和尺寸的复制电路耦合到主推挽放大器电路。 可以使用反馈来偏置复制电路中的晶体管以产生预定的DC输出电压电平，并且可以将这种偏置电平施加到主推挽放大器电路中的相应晶体管。 在另一个实施例中，电流偏置模块中的晶体管可用于偏置主推挽放大器电路和复制电路中的相应晶体管。 公开了用于将放大器配置为具有在较低功率水平下具有更精细分辨率的非均匀步长以及在较高功率水平下较粗分辨率以降低较低功率水平下的功率消耗的技术。

    Switched-Capacitor Circuit Having Two Feedback Capacitors
    3.
    发明申请
    Switched-Capacitor Circuit Having Two Feedback Capacitors 失效
    具有两个反馈电容器的开关电容器电路

    公开(公告)号：US20090185406A1

    公开(公告)日：2009-07-23

    申请号：US12355508

    申请日：2009-01-16

    申请人： Masayuki Uno

    发明人： Masayuki Uno

    IPC分类号： H02M7/537

    CPC分类号： H03F3/005 ,  H03F3/3022 ,  H03F3/45192 ,  H03F3/4565 ,  H03F2203/30084 ,  H03F2203/30099 ,  H03F2203/30117 ,  H03F2203/30132 ,  H03F2203/45616 ,  H03F2203/45726

    摘要： A switched-capacitor circuit performing two-phase operation with a sampling phase and an amplification phase comprising: an inverter having a common source type input transistor and a load transistor; a first capacitor whose first terminal is connected to a gate of the input transistor serving as an input of the inverter; a first switch which connects between the input (the gate of the input transistor) and the output of the inverter, which turns on during the sampling phase and turns off during the amplification phase; a second switch which connects a second terminal of the first capacitor to an input voltage terminal during the sampling phase, and connects the second terminal of the first capacitor to the output terminal of the inverter during the amplification phase; a second capacitor whose first terminal is connected to a gate of the load transistor of the inverter and whose second terminal is connected to the second terminal of the first capacitor; and a third switch which connects the first terminal of the second capacitor to a bias voltage terminal during the sampling phase, and turns off the first terminal of the second capacitor from the bias voltage during the amplification phase.

    摘要翻译： 一种采用采样相位和放大阶段进行两相运算的开关电容电路，包括：具有公共源极型输入晶体管和负载晶体管的反相器; 第一电容器，其第一端子连接到用作反相器的输入的输入晶体管的栅极; 连接在输入（输入晶体管的栅极）和反相器的输出之间的第一开关，其在采样阶段期间导通并在放大阶段期间关断; 第二开关，其在采样阶段期间将第一电容器的第二端子连接到输入电压端子，并且在放大阶段期间将第一电容器的第二端子连接到逆变器的输出端子; 第二电容器，其第一端子连接到逆变器的负载晶体管的栅极，并且其第二端子连接到第一电容器的第二端子; 以及第三开关，其在采样阶段期间将第二电容器的第一端子连接到偏置电压端子，并且在放大阶段期间将第二电容器的第一端子与偏置电压关断。

    Amplifying circuit with variable load drivability
    4.
    发明授权
    Amplifying circuit with variable load drivability 有权
    具有可变负载驱动能力的放大电路

    公开(公告)号：US06885240B2

    公开(公告)日：2005-04-26

    申请号：US10614757

    申请日：2003-07-08

    申请人： You-Jin Cha

    发明人： You-Jin Cha

    IPC分类号： H03K17/687 ,  H03F3/30 ,  H03F3/345 ,  H03F3/45 ,  H03G3/30 ,  H03F3/26

    CPC分类号： H03F3/4521 ,  H03F3/303 ,  H03F2203/30099 ,  H03F2203/30132 ,  H03F2203/7236

    摘要： The present invention relates to an amplifying circuit that can change load drivability responding to load conditions, and reduce power consumption. The amplifying circuit according to the present invention comprises an amplifying means that amplifies input signals a first time to generate a first and a second amplified signals through a first and a second transistors, and further amplifies the first and second amplified signals once again through a third and a fourth transistors, for final outputs; a detecting means for detecting the first and second amplified signals from the amplifying means and generating a first and a second detection signals; and a load drivability control means that is controlled by the first and second detection signals from the detecting means to change load drivability of the amplifying means.

    摘要翻译： 本发明涉及能够根据负载条件改变负载驱动能力并降低功耗的放大电路。 根据本发明的放大电路包括放大装置，其第一次放大输入信号，以通过第一和第二晶体管产生第一和第二放大信号，并且再次通过第三和第三晶体管放大第一和第二放大信号 和第四晶体管，用于最终输出; 检测装置，用于检测来自放大装置的第一和第二放大信号，并产生第一和第二检测信号; 以及由来自检测装置的第一和第二检测信号控制的负载驱动控制装置，以改变放大装置的负载驱动能力。

    Amplifying circuit with variable load drivability
    5.
    发明申请
    Amplifying circuit with variable load drivability 有权
    具有可变负载驱动能力的放大电路

    公开(公告)号：US20040051587A1

    公开(公告)日：2004-03-18

    申请号：US10614757

    申请日：2003-07-08

    发明人： You-Jin Cha

    IPC分类号： H03F003/45

    CPC分类号： H03F3/4521 ,  H03F3/303 ,  H03F2203/30099 ,  H03F2203/30132 ,  H03F2203/7236

    摘要： The present invention relates to an amplifying circuit that can change load drivability responding to load conditions, and reduce power consumption. The amplifying circuit according to the present invention comprises an amplifying means that amplifies input signals a first time to generate a first and a second amplified signals through a first and a second transistors, and further amplifies the first and second amplified signals once again through a third and a fourth transistors, for final outputs; a detecting means for detecting the first and second amplified signals from the amplifying means and generating a first and a second detection signals; and a load drivability control means that is controlled by the first and second detection signals from the detecting means to change load drivability of the amplifying means.

    摘要翻译： 本发明涉及能够根据负载条件改变负载驱动能力并降低功耗的放大电路。 根据本发明的放大电路包括放大装置，其第一次放大输入信号，以通过第一和第二晶体管产生第一和第二放大信号，并且再次通过第三和第三晶体管放大第一和第二放大信号 和第四晶体管，用于最终输出; 检测装置，用于检测来自放大装置的第一和第二放大信号，并产生第一和第二检测信号; 以及由来自检测装置的第一和第二检测信号控制的负载驱动控制装置，以改变放大装置的负载驱动能力。

    DRIVE FOR CASCODE STACK OF POWER FETS
    7.
    发明申请
    DRIVE FOR CASCODE STACK OF POWER FETS 有权
    驱动电源FET的插座堆栈

    公开(公告)号：US20160285454A1

    公开(公告)日：2016-09-29

    申请号：US14671553

    申请日：2015-03-27

    申请人： QUALCOMM Incorporated

    发明人： Vishal Gupta ,  Chifan Yung ,  Joseph Duncan

    IPC分类号： H03K19/0185

    CPC分类号： H03K19/018507 ,  H03F3/2173 ,  H03F2203/30015 ,  H03F2203/30084 ,  H03F2203/30099 ,  H03F2203/30117 ,  H03F2203/30132 ,  H03K17/102

    摘要： Disclosed is a cascode configuration that moves the gate of the cascode substantially without delay relative to an output node by capacitively coupling the latter onto the cascode gates. The passive coupling eliminates the need for actively driving the gates of the cascode. In some embodiments, the only circuitry needed on the cascode gate may be a biasing circuit that limits the swing on the cascode gate between Vmax and 2×Vmax, where Vmax is a transistor device rating.

    摘要翻译： 公开了一种共源共栅结构，其通过将电容耦合到共源共栅电路上而相对于输出节点基本上没有延迟地移动共源共栅的栅极。 无源耦合消除了积极驱动共源共栅的栅极的需要。 在一些实施例中，级联栅极上所需的唯一电路可以是限制Vmax和2×Vmax之间的共源共栅栅极上的摆幅的偏置电路，其中Vmax是晶体管器件额定值。

    Flexible low power slew-rate controlled output buffer
    9.
    发明授权
    Flexible low power slew-rate controlled output buffer 有权
    灵活的低功率转换速率控制输出缓冲器

    公开(公告)号：US08643419B2

    公开(公告)日：2014-02-04

    申请号：US13289068

    申请日：2011-11-04

    申请人： Timothy T. Rueger

    发明人： Timothy T. Rueger

    IPC分类号： H03K5/12

    CPC分类号： H03F3/2171 ,  H03F3/3022 ,  H03F2203/30084 ,  H03F2203/30099 ,  H03F2203/30117 ,  H03F2203/30132

    摘要： An output buffer includes a pullup driver, a pulldown driver, and an output stage. The pullup driver has a drive control input, and an output for providing a pullup drive signal in a push-pull mode in response to receiving a first drive control signal on the drive control input, and in a current limited mode in response to receiving a second drive control signal on said drive control input. The pulldown driver has a drive control input, and an output for providing a pulldown drive signal in the push-pull mode in response to receiving a third drive control signal on the drive control input, and in the current limited mode in response to receiving a fourth drive control signal on the drive control input. The output stage provides a voltage on an output terminal in response to the pullup and pulldown drive signals.

    摘要翻译： 输出缓冲器包括上拉驱动器，下拉驱动器和输出级。 上拉驱动器具有驱动控制输入端和用于响应于在驱动控制输入上接收到第一驱动控制信号而以推挽模式提供上拉驱动信号的输出，并且响应于接收到 所述驱动控制输入上的第二驱动控制信号。 下拉驱动器具有驱动控制输入端，以及用于响应于在驱动控制输入上接收第三驱动控制信号而在推挽模式下提供下拉驱动信号的输出端，以及当前受限模式响应于接收到 驱动控制输入上的第四驱动控制信号。 输出级响应于上拉和下拉驱动信号在输出端子上提供电压。

    FLEXIBLE LOW POWER SLEW-RATE CONTROLLED OUTPUT BUFFER
    10.
    发明申请
    FLEXIBLE LOW POWER SLEW-RATE CONTROLLED OUTPUT BUFFER 有权
    灵活的低功率电力控制输出缓冲器

    公开(公告)号：US20130113524A1

    公开(公告)日：2013-05-09

    申请号：US13289068

    申请日：2011-11-04

    申请人： Timothy T. Rueger

    发明人： Timothy T. Rueger

    IPC分类号： H03K3/00

    CPC分类号： H03F3/2171 ,  H03F3/3022 ,  H03F2203/30084 ,  H03F2203/30099 ,  H03F2203/30117 ,  H03F2203/30132

    摘要： An output buffer includes a pullup driver, a pulldown driver, and an output stage. The pullup driver has a drive control input, and an output for providing a pullup drive signal in a push-pull mode in response to receiving a first drive control signal on the drive control input, and in a current limited mode in response to receiving a second drive control signal on said drive control input. The pulldown driver has a drive control input, and an output for providing a pulldown drive signal in the push-pull mode in response to receiving a third drive control signal on the drive control input, and in the current limited mode in response to receiving a fourth drive control signal on the drive control input. The output stage provides a voltage on an output terminal in response to the pullup and pulldown drive signals.

    摘要翻译： 输出缓冲器包括上拉驱动器，下拉驱动器和输出级。 上拉驱动器具有驱动控制输入端和用于响应于在驱动控制输入上接收到第一驱动控制信号而以推挽模式提供上拉驱动信号的输出，并且响应于接收到 所述驱动控制输入上的第二驱动控制信号。 下拉驱动器具有驱动控制输入端，以及用于响应于在驱动控制输入上接收第三驱动控制信号而在推挽模式下提供下拉驱动信号的输出端，以及当前受限模式响应于接收到 驱动控制输入上的第四驱动控制信号。 输出级响应于上拉和下拉驱动信号在输出端子上提供电压。