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    Semiconductor integrated circuit with self testing and method of testing
    1.
    发明授权
    Semiconductor integrated circuit with self testing and method of testing 有权

    公开(公告)号：US11280831B2

    公开(公告)日：2022-03-22

    申请号：US16800288

    申请日：2020-02-25

    申请人： Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

    发明人： Yuki Watanabe ,  Masato Nakazato ,  Shohei Morishima

    IPC分类号： G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/263

    摘要： According to one embodiment, a semiconductor integrated circuit includes: a first core that includes a first logic circuit that has a plurality of first scan chains, and a first generator that generates a first test pattern; a second core that includes a second logic circuit that has a plurality of second scan chains, and a second generator that generates a second test pattern; a controller that controls a test operation of the first and second cores. The controller is configured to: obtain a seed for a test pattern from the first generator; supply the obtained seed to the second generator; perform a test on the first and second cores for a same number of cycles; obtain first and second test results respectively from the first and second cores; and compare the first and second test results.

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210063489A1

    公开(公告)日：2021-03-04

    申请号：US16797454

    申请日：2020-02-21

    申请人： Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

    发明人： Yuki Watanabe ,  Toshiaki Dozaka

    IPC分类号： G01R31/3185 ,  G01R31/3177

    摘要： According to one embodiment, a semiconductor device includes: a first scan chain and a second scan chain each including a plurality of cascaded flip-flops; a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction; and a clock control circuit that supplies a first clock to the first scan chain and a second clock to the second scan chain, the second clock having timing different to that of the first clock. The plurality of flip-flops are arranged along the second direction.

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11262403B2

    公开(公告)日：2022-03-01

    申请号：US16797454

    申请日：2020-02-21

    申请人： Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

    发明人： Yuki Watanabe ,  Toshiaki Dozaka

    IPC分类号： G01R31/3185 ,  G01R31/3177

    摘要： According to one embodiment, a semiconductor device includes: a first scan chain and a second scan chain each including a plurality of cascaded flip-flops; a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction; and a clock control circuit that supplies a first clock to the first scan chain and a second clock to the second scan chain, the second clock having timing different to that of the first clock. The plurality of flip-flops are arranged along the second direction.