公开(公告)号：US11280831B2

公开(公告)日：2022-03-22

申请号：US16800288

申请日：2020-02-25

Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

Inventor： Yuki Watanabe ,  Masato Nakazato ,  Shohei Morishima

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/263

Abstract: According to one embodiment, a semiconductor integrated circuit includes: a first core that includes a first logic circuit that has a plurality of first scan chains, and a first generator that generates a first test pattern; a second core that includes a second logic circuit that has a plurality of second scan chains, and a second generator that generates a second test pattern; a controller that controls a test operation of the first and second cores. The controller is configured to: obtain a seed for a test pattern from the first generator; supply the obtained seed to the second generator; perform a test on the first and second cores for a same number of cycles; obtain first and second test results respectively from the first and second cores; and compare the first and second test results.

公开(公告)号：US20200300914A1

公开(公告)日：2020-09-24

申请号：US16541277

申请日：2019-08-15

Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

Inventor： Yuki Watanabe ,  Masato Nakazato

IPC: G01R31/3185

Abstract: According to one embodiment, there is provided a circuitry design method. The method includes determining flip-flops for use in constituting a wrapper logic, based on a netlist of circuitry, and forming, after the determining, a multi-bit flip-flop including the flip-flops for use in constituting the wrapper logic, such that a flip-flop which is not used in constituting the wrapper logic is not included in the multi-bit flip-flop.

公开(公告)号：US11262403B2

公开(公告)日：2022-03-01

申请号：US16797454

申请日：2020-02-21

Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

Inventor： Yuki Watanabe ,  Toshiaki Dozaka

IPC: G01R31/3185 ,  G01R31/3177

Abstract: According to one embodiment, a semiconductor device includes: a first scan chain and a second scan chain each including a plurality of cascaded flip-flops; a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction; and a clock control circuit that supplies a first clock to the first scan chain and a second clock to the second scan chain, the second clock having timing different to that of the first clock. The plurality of flip-flops are arranged along the second direction.

公开(公告)号：US10571513B2

公开(公告)日：2020-02-25

申请号：US16122394

申请日：2018-09-05

Applicant: KABUSHIKI KAISHA TOSHIBA ,  Toshiba Electronic Devices & Storage Corporation

Inventor： Masato Nakazato ,  Yuki Watanabe

IPC: G01R31/28 ,  G05F1/565

Abstract: According to one embodiment, there is provided an integrated circuit which includes a power switch including first transistors, and a circuit that outputs information based on impedance according to presence or absence of a fault of at least one transistor among the first transistors.

公开(公告)号：US09620757B2

公开(公告)日：2017-04-11

申请号：US14645846

申请日：2015-03-12

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tetsuro Kano ,  Hiromichi Kuriyama ,  Yuki Watanabe ,  Hidesato Saruwatari ,  Norio Takami

IPC: H01M4/485 ,  H01M4/131 ,  H01M2/16 ,  H01M4/505 ,  H01M4/525 ,  H01M4/36 ,  H01M4/58 ,  H01M4/66 ,  H01M10/0525 ,  H01M10/0567 ,  H01M4/02 ,  H01M10/42

CPC classification number: H01M2/1673 ,  H01M4/131 ,  H01M4/364 ,  H01M4/485 ,  H01M4/505 ,  H01M4/525 ,  H01M4/58 ,  H01M4/661 ,  H01M4/664 ,  H01M4/667 ,  H01M10/0525 ,  H01M10/0567 ,  H01M2004/027 ,  H01M2004/028 ,  H01M2010/4292

Abstract: According to one embodiment, there is provided a nonaqueous electrolyte battery. The nonaqueous electrolyte battery includes a negative electrode, a positive electrode, and a nonaqueous electrolyte. The negative electrode includes an oxide of titanium. The positive electrode includes a positive electrode current collector including aluminum, a positive electrode layer including a nickel-cobalt-manganese composite oxide including lithium, and a passive film formed on the positive electrode current collector. A ratio p/n of a capacity p of the positive electrode to a capacity n of the negative electrode falls within the range from 1.1 to 1.8.

公开(公告)号：US09515298B2

公开(公告)日：2016-12-06

申请号：US14644879

申请日：2015-03-11

Applicant: Kabushiki Kaisha Toshiba

Inventor： Hidesato Saruwatari ,  Hiromichi Kuriyama ,  Tetsuro Kano ,  Yuki Watanabe ,  Norio Takami

IPC: H01M10/052 ,  H01M2/02 ,  H01M4/131 ,  H01M4/485 ,  H01M4/505 ,  H01M4/525 ,  H01M10/0525 ,  H01M4/02

CPC classification number: H01M2/0202 ,  H01M2/024 ,  H01M4/131 ,  H01M4/485 ,  H01M4/505 ,  H01M4/525 ,  H01M10/0525 ,  H01M2004/027 ,  H01M2004/028 ,  Y02E60/122 ,  Y02T10/7011

Abstract: According to one embodiment, a nonaqueous electrolyte battery includes a container, a positive electrode, and a negative electrode. The container satisfies Formula (1) of 0.15≦(Tmin/Tmax)≦1. The positive electrode includes a positive electrode active material represented by the composition formula Li1-aNixCoyMnzO2. The negative electrode includes a spinel type lithium titanium oxide. A nominal capacity of the nonaqueous electrolyte battery is in a range of from 5 Ah to 200 Ah. When a state of charge based on the nominal capacity is 50%, an open circuit voltage is in a range of from 2.12 V to 2.24 V.

Abstract translation: 根据一个实施方案，非水电解质电池包括容器，正极和负极。 容器满足0.15≤（Tmin / Tmax）≤1的式（1）。 正极包括由组成式Li1-aNixCoyMnzO2表示的正极活性物质。 负极包括尖晶石型锂钛氧化物。 非水电解质电池的标称容量在5Ah〜200Ah的范围内。 当基于额定容量的充电状态为50％时，开路电压在2.12V至2.24V的范围内。

公开(公告)号：US12191495B2

公开(公告)日：2025-01-07

申请号：US17466391

申请日：2021-09-03

Applicant: Kabushiki Kaisha Toshiba

Inventor： Tetsuro Kano ,  Yuki Watanabe ,  Hidetoshi Watanabe ,  Keigo Hoshina

IPC: H01M4/00 ,  H01M4/485 ,  H01M4/505 ,  H01M4/525 ,  H01M4/62 ,  H01M10/0525 ,  H01M4/02

Abstract: An electrode includes an active material-containing layer that contains active material particles and a binder containing a polymer. The active material particles contain a lithium-containing nickel-cobalt-manganese composite oxide represented by LiaNi(1−x−y)CoxMnyMzO2 where 0.9≤a≤1.2, 0

公开(公告)号：US11978898B2

公开(公告)日：2024-05-07

申请号：US16807752

申请日：2020-03-03

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tetsuro Kano ,  Dai Yamamoto ,  Yuki Watanabe

IPC: H01M4/505 ,  H01M4/02 ,  H01M4/131 ,  H01M4/36 ,  H01M4/525 ,  H01M4/62 ,  H01M4/66 ,  H01M10/0525 ,  H01M50/46

CPC classification number: H01M4/505 ,  H01M4/131 ,  H01M4/364 ,  H01M4/525 ,  H01M4/623 ,  H01M4/662 ,  H01M10/0525 ,  H01M50/46 ,  H01M2004/021 ,  H01M2004/027 ,  H01M2004/028

Abstract: A positive electrode for nonaqueous electrolyte battery includes specific peaks in pyrolysis GC/MS measurement, and includes specific pore diameters and pore volumes in a pore distribution curve attained by a mercury intrusion method.

公开(公告)号：US11967720B2

公开(公告)日：2024-04-23

申请号：US16806005

申请日：2020-03-02

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yuki Watanabe ,  Dai Yamamoto ,  Toshitada Nakazawa ,  Tetsuro Kano ,  Masanori Tanaka

IPC: H01M4/62 ,  H01M4/02 ,  H01M4/04 ,  H01M4/1391 ,  H01M4/36 ,  H01M4/505 ,  H01M4/525 ,  H01M10/0525

CPC classification number: H01M4/625 ,  H01M4/0404 ,  H01M4/1391 ,  H01M4/364 ,  H01M4/505 ,  H01M4/525 ,  H01M10/0525 ,  H01M2004/021 ,  H01M2004/027 ,  H01M2004/028

Abstract: An electrode according to an embodiment contains an electrode mixture layer containing an active material and a conductive assistant. In a logarithmic differential pore volume distribution by a mercury intrusion method, the electrode mixture layer satisfies: a ratio P1/P2 within a range of 2 or more and less than 8, and a ratio S1/S2 within a range of 3 or more and less than 10. P1 is a value of a maximum logarithmic differential pore volume in a pore diameter range of 0.1 μm or more and 1 μm or less. P2 is a value of a logarithmic differential pore volume of a pore diameter of 0.03 μm. S1 is an integrated value in a pore diameter range of 0.1 μm or more and 1 μm or less. S2 is an integrated value in a pore diameter range of more than 0 μm and less than 0.1 μm.

公开(公告)号：US20210063489A1

公开(公告)日：2021-03-04

申请号：US16797454

申请日：2020-02-21

Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

Inventor： Yuki Watanabe ,  Toshiaki Dozaka

IPC: G01R31/3185 ,  G01R31/3177

Abstract: According to one embodiment, a semiconductor device includes: a first scan chain and a second scan chain each including a plurality of cascaded flip-flops; a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction; and a clock control circuit that supplies a first clock to the first scan chain and a second clock to the second scan chain, the second clock having timing different to that of the first clock. The plurality of flip-flops are arranged along the second direction.