公开(公告)号：US20240347087A1

公开(公告)日：2024-10-17

申请号：US18754823

申请日：2024-06-26

Applicant: KIOXIA CORPORATION

Inventor： Zhao LU ,  Yuji NAGAI ,  Akio SUGAHARA ,  Takehisa KUROSAWA ,  Masaru KOYANAGI

IPC: G11C7/22 ,  G11C7/08 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/08 ,  G11C7/1063 ,  G11C7/109

Abstract: A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.

公开(公告)号：US20230282257A1

公开(公告)日：2023-09-07

申请号：US17898981

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Takehisa KUROSAWA ,  Akio SUGAHARA ,  Mitsuhiro ABE ,  Hisashi FUJIKAWA ,  Yuji NAGAI ,  Zhao LU

IPC: G11C7/22 ,  G11C7/20 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/20 ,  G11C7/1069

Abstract: A memory system includes a memory controller and a semiconductor storage device including a power supply pad, first, second, third, and fourth signal pads to which first, second, third, and fourth signals are respectively input, a memory cell array, a data register, and a control circuit executing an operation to output data stored in the data register through the fourth signal pad. The memory controller performs a mode setting operation by toggling the third signal input, after at least the first or second signal has been switched at a first timing after supplying power to the power supply pad, perform an initial setting operation by transmitting a power-on read command at a second timing after the first timing, and transmit a data-out command, at a third timing after the second timing. The semiconductor storage device receives the power-on read and data-out commands via the first and second signal pads.

公开(公告)号：US20230022082A1

公开(公告)日：2023-01-26

申请号：US17806965

申请日：2022-06-15

Applicant: KIOXIA CORPORATION

Inventor： Zhao LU ,  Yuji NAGAI ,  Akio SUGAHARA ,  Takehisa KUROSAWA ,  Masaru KOYANAGI

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/08

Abstract: A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.

公开(公告)号：US20220317932A1

公开(公告)日：2022-10-06

申请号：US17464791

申请日：2021-09-02

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Zhao LU ,  Takehisa KUROSAWA ,  Yuji NAGAI

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/26

Abstract: A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.

公开(公告)号：US20240094959A1

公开(公告)日：2024-03-21

申请号：US18524477

申请日：2023-11-30

Applicant: KIOXIA CORPORATION

Inventor： Akio SUGAHARA ,  Zhao LU ,  Takehisa KUROSAWA ,  Yuji NAGAI

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/26

Abstract: A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.