公开(公告)号：US20220334734A1

公开(公告)日：2022-10-20

申请号：US17583019

申请日：2022-01-24

Applicant: Kioxia Corporation

Inventor： Hisashi FUJIKAWA

IPC: G06F3/06 ,  G06F21/31 ,  G06F21/60

Abstract: An information processing system includes a host and a memory system. A processor of the host is configured to: determine a logical address of read data and a size of the read data; prepare third information related to the read data other than the logical address of the read data and the size of the read data, the third information being information necessary for the memory system to transmit the read data to the host; and transmit, to the memory system, a command requesting to transmit the read data. A memory controller of the memory system is configured to, in response to receiving the command from the host, transmit a request for the third information to the host. The processor of the host is further configured to, in response to receiving the request from the memory system, transmit the third information to the memory system. The memory controller of the memory system is further configured to, by using the third information, acquire the read data from a nonvolatile memory and transmit the acquired read data to the host, without receiving another command from the host.

公开(公告)号：US20230282257A1

公开(公告)日：2023-09-07

申请号：US17898981

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Takehisa KUROSAWA ,  Akio SUGAHARA ,  Mitsuhiro ABE ,  Hisashi FUJIKAWA ,  Yuji NAGAI ,  Zhao LU

IPC: G11C7/22 ,  G11C7/20 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/20 ,  G11C7/1069

Abstract: A memory system includes a memory controller and a semiconductor storage device including a power supply pad, first, second, third, and fourth signal pads to which first, second, third, and fourth signals are respectively input, a memory cell array, a data register, and a control circuit executing an operation to output data stored in the data register through the fourth signal pad. The memory controller performs a mode setting operation by toggling the third signal input, after at least the first or second signal has been switched at a first timing after supplying power to the power supply pad, perform an initial setting operation by transmitting a power-on read command at a second timing after the first timing, and transmit a data-out command, at a third timing after the second timing. The semiconductor storage device receives the power-on read and data-out commands via the first and second signal pads.

公开(公告)号：US20230066699A1

公开(公告)日：2023-03-02

申请号：US17809114

申请日：2022-06-27

Applicant: KIOXIA CORPORATION

Inventor： Zhao LYU ,  Akio SUGAHARA ,  Takehisa KUROSAWA ,  Yuji NAGAI ,  Hisashi FUJIKAWA

IPC: G11C7/10 ,  G11C8/06

Abstract: A memory system includes semiconductor memory devices and a control device. Each of the semiconductor memory devices includes a first pad to which a first signal is input, a second pad to which a second signal is input, a third pad to which a third signal is input, a memory cell array, a sense amplifier, and a data register. In a first mode, after the first signal is switched, a command set instructing a data out operation is input via the second pad. In a second mode, after the first signal is switched, the command is input via at least the third pad. The control device executes a first operation assigning different addresses to the respective semiconductor memory devices and a second operation causing the modes of the respective semiconductor memory devices to be switched from the first to the second mode.

公开(公告)号：US20250053334A1

公开(公告)日：2025-02-13

申请号：US18797852

申请日：2024-08-08

Applicant: Kioxia Corporation

Inventor： Hisashi FUJIKAWA

IPC: G06F3/06

Abstract: According to one embodiment, a memory system includes a nonvolatile memory chip, a buffer, and a controller. The nonvolatile memory chip includes a memory cell array. The buffer is capable of storing data received in accordance with receiving a write request from a host. In a case where a piece of data of a first size is written in a write operation for the nonvolatile memory chip, the controller performs a data transfer operation of transferring a piece of data of a second size smaller than the first size from the buffer to the nonvolatile memory chip multiple times. The controller writes, into the memory cell array, pieces of data of the second size transferred to the nonvolatile memory chip by performing the data transfer operation the multiple times, respectively.

公开(公告)号：US20250110870A1

公开(公告)日：2025-04-03

申请号：US18820110

申请日：2024-08-29

Applicant: Kioxia Corporation

Inventor： Naoki HOSOYAMA ,  Hisashi FUJIKAWA

IPC: G06F12/02 ,  G06F13/16

Abstract: A controller sets a designated region for a data size, which has consecutive physical addresses, in a storage region of a first memory and stores in a second memory address conversion information in which a head physical address of the consecutive physical addresses is associated with a head logical address of consecutive logical addresses and the data size, in response to a region designation command to which the consecutive logical addresses and the data size are assigned, from a host device. The controller, in response to a read command received from the host device that has a logical address assigned thereto and correspond to data stored in the designated region, determines a physical address corresponding to the logical address assigned to the read command, using the address conversion information stored in the second memory.

公开(公告)号：US20240028199A1

公开(公告)日：2024-01-25

申请号：US18481849

申请日：2023-10-05

Applicant: Kioxia Corporation

Inventor： Hisashi FUJIKAWA

IPC: G06F3/06

CPC classification number: G06F3/0607 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679

Abstract: According to one embodiment, a memory system includes an array of memory cells that store two or more bits of data each, and a memory controller to control writing data into the memory cells and reading from the memory cells. When a first command is received from a host, the memory controller reads data designated by the first command from the array and then rewrites the read data back into the array using a writing method in which a lower number of bits per memory cell is written than the originally stored manner of the read data. When a read command designating the rewritten data is received from the host, the memory controller reads from the array and transfers it to the host.