公开(公告)号：US20240347087A1

公开(公告)日：2024-10-17

申请号：US18754823

申请日：2024-06-26

Applicant: KIOXIA CORPORATION

Inventor： Zhao LU ,  Yuji NAGAI ,  Akio SUGAHARA ,  Takehisa KUROSAWA ,  Masaru KOYANAGI

IPC: G11C7/22 ,  G11C7/08 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/08 ,  G11C7/1063 ,  G11C7/109

Abstract: A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.

公开(公告)号：US20240094959A1

公开(公告)日：2024-03-21

申请号：US18524477

申请日：2023-11-30

Applicant: KIOXIA CORPORATION

Inventor： Akio SUGAHARA ,  Zhao LU ,  Takehisa KUROSAWA ,  Yuji NAGAI

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/26

Abstract: A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.

公开(公告)号：US20230282257A1

公开(公告)日：2023-09-07

申请号：US17898981

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Takehisa KUROSAWA ,  Akio SUGAHARA ,  Mitsuhiro ABE ,  Hisashi FUJIKAWA ,  Yuji NAGAI ,  Zhao LU

IPC: G11C7/22 ,  G11C7/20 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/20 ,  G11C7/1069

Abstract: A memory system includes a memory controller and a semiconductor storage device including a power supply pad, first, second, third, and fourth signal pads to which first, second, third, and fourth signals are respectively input, a memory cell array, a data register, and a control circuit executing an operation to output data stored in the data register through the fourth signal pad. The memory controller performs a mode setting operation by toggling the third signal input, after at least the first or second signal has been switched at a first timing after supplying power to the power supply pad, perform an initial setting operation by transmitting a power-on read command at a second timing after the first timing, and transmit a data-out command, at a third timing after the second timing. The semiconductor storage device receives the power-on read and data-out commands via the first and second signal pads.

公开(公告)号：US20210082536A1

公开(公告)日：2021-03-18

申请号：US17009404

申请日：2020-09-01

Applicant: Kioxia Corporation

Inventor： Takehisa KUROSAWA ,  Koichi Shinohara ,  Yusuke Tanefusa

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/14 ,  G11C29/42

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a processing circuit, a timer, a command decoder, and a training circuit. The memory cell array includes a plurality of memory cells. The processing circuit writes data into the memory cell array. The timer sets a waiting time. The command decoder receives a command output from a memory controller. The training circuit waits until the waiting time has passed since a predetermined command is received by the command decoder and performs a process relating to determination of a correction value for a signal sent from the memory controller to the processing circuit based on reference data output from the memory controller after the waiting time has passed.

公开(公告)号：US20210375337A1

公开(公告)日：2021-12-02

申请号：US17189604

申请日：2021-03-02

Applicant: KIOXIA CORPORATION

Inventor： Takehisa KUROSAWA

IPC: G11C7/10 ,  G11C7/12

Abstract: A memory system includes a memory chip, one or more signal lines including a first signal line, and a controller. The controller is connected to the memory chip via the one or more signal lines. The controller is configured to transmit and receive signals via the first signal line in accordance with a first standard under which voltages of communicated signals transition in a first range and with a second standard under which voltages of communicated signals transition in a second range narrower than the first range. The controller is configured to transmit a command to the memory chip via the first signal line in accordance with the first standard, and based on a response to the command from the memory chip, enable communication in accordance with the second standard.

公开(公告)号：US20210241812A1

公开(公告)日：2021-08-05

申请号：US17160885

申请日：2021-01-28

Applicant: Kioxia Corporation

Inventor： Takehisa KUROSAWA ,  Yusuke TANEFUSA

IPC: G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/411

Abstract: A memory system includes a semiconductor storage device, a power supply circuit that generates a first power, and a memory controller that operates based on the first power and transmits a command to the semiconductor storage device. The semiconductor storage device includes a first terminal, a second terminal, a word line, a first circuit, and a second circuit. The first power is input to the first terminal. A second power that can be used even after a voltage of the first terminal decreases is input to the second terminal. The word line is connected to a control gate of a memory cell transistor. The first circuit applies a voltage according to the command to the word line based on the first power input to the first terminal. The second circuit discharges charges of the word line by using the second power input to the second terminal when a voltage of the first terminal decreases.

公开(公告)号：US20230066699A1

公开(公告)日：2023-03-02

申请号：US17809114

申请日：2022-06-27

Applicant: KIOXIA CORPORATION

Inventor： Zhao LYU ,  Akio SUGAHARA ,  Takehisa KUROSAWA ,  Yuji NAGAI ,  Hisashi FUJIKAWA

IPC: G11C7/10 ,  G11C8/06

Abstract: A memory system includes semiconductor memory devices and a control device. Each of the semiconductor memory devices includes a first pad to which a first signal is input, a second pad to which a second signal is input, a third pad to which a third signal is input, a memory cell array, a sense amplifier, and a data register. In a first mode, after the first signal is switched, a command set instructing a data out operation is input via the second pad. In a second mode, after the first signal is switched, the command is input via at least the third pad. The control device executes a first operation assigning different addresses to the respective semiconductor memory devices and a second operation causing the modes of the respective semiconductor memory devices to be switched from the first to the second mode.

公开(公告)号：US20230022082A1

公开(公告)日：2023-01-26

申请号：US17806965

申请日：2022-06-15

Applicant: KIOXIA CORPORATION

Inventor： Zhao LU ,  Yuji NAGAI ,  Akio SUGAHARA ,  Takehisa KUROSAWA ,  Masaru KOYANAGI

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/08

Abstract: A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.

公开(公告)号：US20220317932A1

公开(公告)日：2022-10-06

申请号：US17464791

申请日：2021-09-02

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Zhao LU ,  Takehisa KUROSAWA ,  Yuji NAGAI

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/26

Abstract: A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.