公开(公告)号：US20250107069A1

公开(公告)日：2025-03-27

申请号：US18884101

申请日：2024-09-12

Applicant: Kioxia Corporation

Inventor： Takeru MAEDA ,  Sakuya KANEKO ,  Kenichiro TORATANI ,  Takafumi OCHIAI ,  Kazuhiro MATSUO ,  Masaya TODA ,  Ha HOANG ,  Kotaro NODA

IPC: H10B12/00 ,  H01L29/786

Abstract: According to one embodiment a semiconductor device includes an oxide semiconductor column that extends in a first direction. A first electrode contacts a first end of the oxide semiconductor column and a second electrode contacts a second end. A gate electrode surrounds a portion of the oxide semiconductor column. A first insulating film is between the gate electrode and the oxide semiconductor column. A second insulating film is between the gate electrode and the first electrode in the first direction and surrounds the oxide semiconductor column via the first insulating film. A region in which at least a part of the oxide semiconductor column is accommodated is formed by the gate electrode and the second insulating film, and the region has a stepped surface facing towards the second electrode.

公开(公告)号：US20210296583A1

公开(公告)日：2021-09-23

申请号：US17021655

申请日：2020-09-15

Applicant: Kioxia Corporation

Inventor： Hiroyuki ODE ,  Kotaro NODA

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor memory device includes a first wiring to a fifth wiring, a plurality of memory cells disposed between the wirings, and a first contact electrode to a third contact electrode. The first contact electrode is disposed between the first wiring and the fifth wiring, and is electrically connected to the first wiring and the fifth wiring. The second contact electrode is disposed between the first contact electrode and the fifth wiring, and is electrically connected to the first wiring and the fifth wiring. The third contact electrode is disposed between the second contact electrode and the fifth wiring, and is electrically connected to the first wiring and the fifth wiring. The second contact electrode has a width larger than a width of the first contact electrode and larger than a width of the third contact electrode.

公开(公告)号：US20240315007A1

公开(公告)日：2024-09-19

申请号：US18592970

申请日：2024-03-01

Applicant: Kioxia Corporation

Inventor： Kotaro NODA ,  Takahiro FUJII ,  Takanori AKITA ,  Mutsumi OKAJIMA

IPC: H10B12/00

CPC classification number: H10B12/33 ,  H10B12/05

Abstract: A semiconductor device includes a first oxide semiconductor layer extending in a first direction, a first wiring extending in a second direction that intersects the first direction and surrounding the first oxide semiconductor layer, a first insulating film provided between the first wiring and the first oxide semiconductor layer, a first conductor provided on the first oxide semiconductor layer, a second wiring provided on the first conductor and extending in a third direction that intersects each of the first direction and the second direction, a first insulating layer in contact with a side surface of the second wiring, and a second insulating layer provided on the first insulating layer and having oxygen permeability lower than oxygen permeability of the first insulating layer.

公开(公告)号：US20220302378A1

公开(公告)日：2022-09-22

申请号：US17461029

申请日：2021-08-30

Applicant: Kioxia Corporation

Inventor： Kotaro NODA ,  Kyoko NODA ,  Ken HOSHINO ,  Shuichi TSUBATA

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

Abstract: A semiconductor memory device includes a first interconnect, a second interconnect, a first storage layer, and a first insulating film. The first insulating film is provided along a surface of a part of the second interconnect and a surface of the first storage layer. The first insulating film is composed of Si, N, and O. The atomic ratio (N/O) between N and O in the first insulating film is not less than 1.0 at a first position which is the position of the second interconnect-side end surface of the first storage layer in a third direction. The atomic ratio (N/O) between N and O in the first insulating film is less than 1.0 at a second position which is the position of the end surface of the second interconnect, opposite to the first storage layer-side end surface, in the third direction.

公开(公告)号：US20220263024A1

公开(公告)日：2022-08-18

申请号：US17738668

申请日：2022-05-06

Applicant: Kioxia Corporation

Inventor： Kotaro NODA

IPC: H01L45/00 ,  H01L27/24

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films.

公开(公告)号：US20250089237A1

公开(公告)日：2025-03-13

申请号：US18595558

申请日：2024-03-05

Applicant: Kioxia Corporation

Inventor： Takeru MAEDA ,  Shosuke FUJII ,  Kotaro NODA

IPC: H10B12/00

Abstract: A semiconductor device includes: an oxide semiconductor including a first end and a second end and extending in a first direction oriented from the second end to the first end; a first electrode configured to come into contact with the first end of the oxide semiconductor; a second electrode configured to come into contact with the second end of the oxide semiconductor; a gate electrode configured to enclose the oxide semiconductor with a first insulating film interposed therebetween between the first and second ends of the oxide semiconductor; and a metal film including a cylindrical portion that comes into contact with the gate electrode in the first direction and encloses the oxide semiconductor with the first insulating film interposed therebetween.

公开(公告)号：US20240322045A1

公开(公告)日：2024-09-26

申请号：US18593038

申请日：2024-03-01

Applicant: Kioxia Corporation

Inventor： Takanori AKITA ,  Kotaro NODA ,  Takahiro FUJII ,  Kasumi OKABE

IPC: H01L29/786 ,  H10B12/00

CPC classification number: H01L29/7869 ,  H10B12/30 ,  H10B12/05 ,  H10B12/50

Abstract: A semiconductor device includes a first insulating layer; an oxide semiconductor formed in the first insulating layer, extending in a first direction, and having a first end and a second end; a first electrode including a first metal film that includes a first metal atom, and a first conductive film that is formed between the first metal film and the first end of the oxide semiconductor and includes metal oxide; a second electrode in contact with the second end of the oxide semiconductor; at least a pair of gate electrodes that face each other via an insulating film, and are interposed between the first end and the second end of the oxide semiconductor; and a first structure that is separated from the first electrode in a second direction intersecting the first direction, includes at least the first metal atom, and does not include the metal oxide.

公开(公告)号：US20240015950A1

公开(公告)日：2024-01-11

申请号：US18179546

申请日：2023-03-07

Applicant: Kioxia Corporation

Inventor： Masayuki MURASE ,  Kotaro NODA

IPC: H10B12/00 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B12/33 ,  H10B12/036 ,  H01L29/66742 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a channel filling a through via hole and including an oxide semiconductor; a first electrode disposed on the channel and formed of a conductive oxide; and a second electrode disposed on the first electrode and formed of a metal.

公开(公告)号：US20230422482A1

公开(公告)日：2023-12-28

申请号：US18338837

申请日：2023-06-21

Applicant: Kioxia Corporation

Inventor： Shosuke FUJII ,  Kotaro NODA

IPC: H10B12/00

CPC classification number: H10B12/33 ,  H10B12/05

Abstract: A semiconductor device according to an embodiment includes: a first electrode; a second electrode; a gate electrode between the first electrode and the second electrode; a first insulating layer; a second insulating layer; a gate insulating layer surrounding the gate electrode; an oxide semiconductor layer surrounding the gate insulating layer, the oxide semiconductor layer including a first region between the gate insulating layer and the first electrode, a second region between the gate insulating layer and the second electrode, a third region between the gate insulating layer and the first insulating layer, and a fourth region between the gate insulating layer and the second insulating layer. A first thickness of the first region and a second thickness of the second region are equal to or less than at least one of a third thickness of the third region or a fourth thickness of the fourth region.

公开(公告)号：US20230309294A1

公开(公告)日：2023-09-28

申请号：US17901772

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Mutsumi OKAJIMA ,  Nobuyoshi SAITO ,  Keiji IKEDA ,  Kotaro NODA ,  Takanori AKITA

IPC: H01L27/108

CPC classification number: H01L27/1082 ,  H01L27/10897 ,  H01L27/10873

Abstract: A semiconductor device includes: an oxide semiconductor layer extending in a first direction; a gate electrode overlapping the oxide semiconductor layer in a second direction intersecting the first direction; a gate insulating film provided between the gate electrode and the oxide semiconductor layer; a first conductive layer provided on the oxide semiconductor layer in the first direction and containing a conductive oxide; a second conductive layer provided on the first conductive layer in the first direction and containing a metal element; a first protective film in contact with a side surface of the second conductive layer; and a second protective film in contact with at least a part of a side surface or an upper surface of the first conductive layer. The first protective film and the second protective film each contain a material having an oxygen diffusion coefficient smaller than that of the second conductive layer.