公开(公告)号：US20220068925A1

公开(公告)日：2022-03-03

申请号：US17193941

申请日：2021-03-05

Applicant: Kioxia Corporation

Inventor： Hiroki KAWAI ,  Junji KATAOKA ,  Keiji IKEDA

IPC: H01L27/108 ,  H01L29/24 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device of an embodiment includes an oxide semiconductor layer. The oxide semiconductor layer includes a metal oxide containing at least one first metal element selected from the group consisting of indium and tin and at least one second metal element selected from the group consisting of zinc, gallium, aluminum, tungsten, and silicon. The oxide semiconductor layer includes a first region in which at least one anion element selected from the group consisting of fluorine and chlorine is contained within a range of 1 atomic % or more and less than 8 atomic % in the metal oxide.

公开(公告)号：US20240260253A1

公开(公告)日：2024-08-01

申请号：US18423110

申请日：2024-01-25

Applicant: Kioxia Corporation

Inventor： Mutsumi OKAJIMA ,  Takafumi MASUDA ,  Nobuyoshi SAITO ,  Keiji IKEDA

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05

Abstract: A semiconductor memory device comprises: a substrate;
memory layers arranged in a first direction intersecting with a surface of the substrate; and a first via wiring extending in the first direction. The memory layers each comprise: a first semiconductor layer electrically connected to the first via wiring; a first gate electrode facing surfaces on one side and the other side in the first direction of the first semiconductor layer; a memory portion which is provided on one side in a second direction intersecting with the first direction with respect to the first semiconductor layer, and is electrically connected to the first semiconductor layer; and a first wiring which is provided on the other side in the second direction with respect to the first semiconductor layer, is electrically connected to the first gate electrode, and extends in a third direction intersecting with the first direction and the second direction.

公开(公告)号：US20230301065A1

公开(公告)日：2023-09-21

申请号：US17901077

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Mutsumi OKAJIMA ,  Keiji IKEDA

IPC: H01L27/108 ,  G11C11/4091

CPC classification number: H01L27/10811 ,  G11C11/4091 ,  H01L27/10873

Abstract: A semiconductor memory device includes: a plate electrode; a plurality of memory capacitors arranged along a front surface of the plate electrode; and a plurality of memory transistors electrically connected to the plurality of memory capacitors. Each memory capacitor includes: a columnar first electrode electrically connected to the memory transistor; a dielectric layer provided on an outer periphery of the first electrode; a second electrode provided on an outer periphery of the dielectric layer and electrically connected to the plate electrode; and an insulating layer provided between the first electrode and the plate electrode and containing a material that is different from a material contained in the dielectric layer.

公开(公告)号：US20220085182A1

公开(公告)日：2022-03-17

申请号：US17198673

申请日：2021-03-11

Applicant: Kioxia Corporation

Inventor： Junji KATAOKA ,  Tomomasa UEDA ,  Shushu ZHENG ,  Nobuyoshi SAITO ,  Keiji IKEDA

IPC: H01L29/423 ,  H01L27/108 ,  H01L29/22 ,  H01L29/786

Abstract: A semiconductor device according to an embodiment includes an oxide semiconductor layer, a gate electrode, and the gate electrode, a first electrode electrically connected to the oxide semiconductor layer, a second electrode electrically connected to the oxide semiconductor layer, a first conductive layer provided at at least one position between the oxide semiconductor layer and the first electrode and between the oxide semiconductor layer and the second electrode, the first conductive layer containing a first metal element, a first element different from the first metal element, and one of oxygen (O) or nitrogen (N), and a second conductive layer between the oxide semiconductor layer and the first conductive layer, the second conductive layer containing oxygen (O) and a second element different from both of the first metal element and the first element. The gate electrode is between the first electrode and the second electrode in the first direction.

公开(公告)号：US20210249540A1

公开(公告)日：2021-08-12

申请号：US17001208

申请日：2020-08-24

Applicant: Kioxia Corporation

Inventor： Shigeki HATTORI ,  Tomomasa UEDA ,  Keiji IKEDA

IPC: H01L29/786 ,  H01L27/108 ,  H01L27/12 ,  H01L29/24

Abstract: A semiconductor device of an embodiment includes: a first oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region; a gate electrode; a gate insulating layer provided between the third region and the gate electrode; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; and a second oxide semiconductor layer provided in at least one of a position between the first region and the first electrode and a position between the second region and the second electrode and containing indium (In), aluminum (Al), and zinc (Zn), an atomic ratio of aluminum to a sum of indium, aluminum, and zinc being 8% or more and 23% or less, and an atomic ratio of indium to the sum of indium, aluminum, and zinc being 45% or less.

公开(公告)号：US20250070024A1

公开(公告)日：2025-02-27

申请号：US18811335

申请日：2024-08-21

Applicant: Kioxia Corporation

Inventor： Takafumi MASUDA ,  Mutsumi OKAJIMA ,  Nobuyoshi SAITO ,  Keiji IKEDA

IPC: H01L23/528 ,  H01L23/522 ,  H10B53/10 ,  H10B53/20

Abstract: A semiconductor memory device includes a substrate, first semiconductor layers stacked in a first direction intersecting the substrate, a first via wiring extending in the direction and connected to the layers, memory units stacked in the direction and connected to the layers, first gate electrodes stacked in the direction and facing the layers, first wirings stacked in the direction, extending in a second direction intersecting the first direction, and connected to the first electrodes, second semiconductor layers stacked in the first direction and connected to the first electrodes via the first wirings, a second via wiring extending in the first direction and connected to the second layers, and second gate electrodes stacked in the first direction and facing the second layers. The second layers include a different material from the first layers, or a composition ratio of materials of the second layers is different from that of the first layers.

公开(公告)号：US20220085212A1

公开(公告)日：2022-03-17

申请号：US17198682

申请日：2021-03-11

Applicant: Kioxia Corporation

Inventor： Yuta SATO ,  Tomomasa UEDA ,  Nobuyoshi SAITO ,  Keiji IKEDA

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/24 ,  H01L27/13

Abstract: A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.

公开(公告)号：US20200381557A1

公开(公告)日：2020-12-03

申请号：US16809199

申请日：2020-03-04

Applicant: Kioxia Corporation

Inventor： Shigeki HATTORI ,  Tomomasa UEDA ,  Keiji IKEDA

IPC: H01L29/786 ,  H01L27/108

Abstract: According to an embodiment, a semiconductor device includes an oxide semiconductor layer including indium (In), aluminum (Al), and zinc (Zn), the oxide semiconductor layer having an atomic ratio of the aluminum to a sum of indium, aluminum, and zinc of equal to or more than 8% and equal to or less than 23%, a gate electrode, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode.

公开(公告)号：US20240324174A1

公开(公告)日：2024-09-26

申请号：US18605986

申请日：2024-03-15

Applicant: Kioxia Corporation

Inventor： Takafumi MASUDA ,  Mutsumi OKAJIMA ,  Nobuyoshi SAITO ,  Keiji IKEDA

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05

Abstract: A semiconductor memory device includes memory layers arranged in a first direction and a via-wiring extending in the first direction. The plurality of memory layers each include a semiconductor layer electrically connected to the via-wiring, a gate electrode opposed to surfaces of the semiconductor layer in the first direction, a memory portion disposed on one side in a second direction with respect to the semiconductor layer, a wiring disposed on the other side in the second direction with respect to the semiconductor layer, and a connection wiring connected to the gate electrode and the wiring. The connection wiring includes a first part extending in the second direction along a side surface of the gate electrode in the third direction and a second part continuous with the first part, extending in the third direction along a side surface of the wiring in the second direction.

公开(公告)号：US20240312911A1

公开(公告)日：2024-09-19

申请号：US18601745

申请日：2024-03-11

Applicant: Kioxia Corporation

Inventor： Takafumi MASUDA ,  Mutsumi OKAJIMA ,  Nobuyoshi SAITO ,  Keiji IKEDA

IPC: H01L23/528 ,  H01L23/522 ,  H10B12/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L23/528 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor memory device includes a memory layer and a via-wiring extending in a first direction. The memory layer includes a semiconductor layer electrically connected to the via-wiring, a gate electrode including parts opposed to surfaces of the semiconductor layer on one side and the other side in the first direction, a memory portion disposed on one side in a second direction with respect to the semiconductor layer, and a wiring disposed on the other side in the second direction with respect to the semiconductor layer. In a cross-sectional surface perpendicular to the first direction and including one of the parts of the gate electrode, the via-wiring includes a surface opposed to the gate electrode and a surface not opposed to the gate electrode. A part of the gate electrode is disposed on a memory portion side with respect to the via-wiring in the second direction.