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公开(公告)号：US20130146684A1
公开(公告)日：2013-06-13
申请号：US13818543
申请日：2011-08-31
申请人： Kouichi Minakuchi , Aoi Shinohara , Tomohiko Tsutsumi , Natsumi Yukawa , Akira Nagamori , Satoshi Kishimoto , Makoto Ide , Kouei Obata , Mamoru Okumoto , Masashi Kamada
发明人： Kouichi Minakuchi , Aoi Shinohara , Tomohiko Tsutsumi , Natsumi Yukawa , Akira Nagamori , Satoshi Kishimoto , Makoto Ide , Kouei Obata , Mamoru Okumoto , Masashi Kamada
IPC分类号： B05B5/00
CPC分类号： B05B5/00 , B05B5/057 , B05B9/0805 , B05B12/12 , F24F6/12
摘要： An electrostatic sprayer includes a temperature-humidity sensor which detects a humidity and a temperature of a space where the user is present, and a control section which provides control by adjusting an amount of the liquid transferred by a pressure pump and a voltage applied by a high voltage power supply based on the value detected by the temperature-humidity sensor.
摘要翻译： 静电喷雾器包括：温度 - 湿度传感器，其检测使用者存在的空间的湿度和温度;以及控制部，其通过调节由压力泵传递的液体的量和由 基于温湿度传感器检测到的高电压电源。
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2.发明申请High-speed interface circuit test module, module under high-speed interface circuit test, and high-speed interface circuit test method 审中-公开高速接口电路测试模块，模块高速接口电路测试，高速接口电路测试方法公开(公告)号：US20050258856A1
公开(公告)日：2005-11-24
申请号：US11133290
申请日：2005-05-20
IPC分类号： G01R31/28 , G01R31/26 , G01R31/30 , G01R31/317 , G01R31/319 , G06F13/00 , H04L12/26
CPC分类号： G01R31/31905 , G01R31/3016 , G01R31/31712 , G01R31/31926 , H04L43/50
摘要： In the shipment test of an LSI provided with a high-speed interface circuit, both cost reduction and a high test guarantee level are realized. The following are provided: a high-speed interface circuit that is mounted on a load board interfacing with an LSI tester, is provided with a circuit converting the signal speed, and is capable of changing the transmission and reception characteristics; a controller that controls the transmission and reception characteristics of the high-speed interface circuit; a clock generator that generates the clock supplied to the high-speed interface circuit; a first connector provided specifically for the high-speed interface, connected to the high-speed interface circuit and provided with a signal port for performing high-speed signal communication with a circuit under test; and a second connector connected to the high-speed interface circuit and the LSI tester and provided with a signal port and a power port for performing low-speed signal communication with the high-speed interface circuit.
摘要翻译： 在具有高速接口电路的LSI的出货测试中，实现了成本降低和高测试保证水平。 提供以下内容：安装在与LSI测试器接口的负载板上的高速接口电路设置有转换信号速度的电路，并且能够改变发送和接收特性; 控制器，其控制高速接口电路的发送和接收特性; 产生提供给高速接口电路的时钟的时钟发生器; 专为高速接口而设计的第一连接器，连接到高速接口电路并且设置有用于与被测电路进行高速信号通信的信号端口; 以及连接到高速接口电路和LSI测试器的第二连接器，并且设置有用于与高速接口电路进行低速信号通信的信号端口和电源端口。
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公开(公告)号：US08296972B2
公开(公告)日：2012-10-30
申请号：US12414141
申请日：2009-03-30
IPC分类号： A43B23/00
CPC分类号： A43B23/047 , A43B1/04 , A43B9/12
摘要： A shoe 1 of the present invention includes an upper 2 made of a stretchable fabric. The stretchable fabric is integrated with a sole 3 in a state of being stretched. Further, a method of manufacturing the shoe 1 of the present invention is a method of manufacturing a shoe using a stretchable fabric for the upper 2. The method includes steps of: producing an upper pattern using a last having a size smaller than that of the sole 3 as a base; producing the upper 2 with the stretchable fabric being stretched by stretching the upper pattern and fitting the upper pattern onto a last having a size that matches the sole 3; and integrating the upper 2 with the stretchable fabric being stretched with the sole 3.
摘要翻译： 本发明的鞋1包括由可伸缩织物制成的鞋面2。 伸缩性织物与被拉伸状态的鞋底3一体化。 此外，制造本发明的鞋1的方法是使用上部2的伸缩性织物制造鞋子的方法。该方法包括以下步骤：使用具有小于 鞋底3为基地; 通过拉伸上部图案并将上部图案装配到具有与鞋底3相匹配的尺寸的最后部分上，使可伸展织物拉伸; 并且将上部2与被鞋底3拉伸的可伸展织物整合。
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公开(公告)号：US4878217A
公开(公告)日：1989-10-31
申请号：US150855
申请日：1988-02-01
摘要： In a data outputting device, data to be outputted is digitally stored in a memory and is read out when addressed over a predetermined period in a time division multiplex mode with addresses which are provided by a counter in such a manner that the number thereof of addresses provided per predetermined time period corresponds to the number of channels employed, and the data thus read out with the addresses are selected for the channels by a selection circuit, respectively, so that they are outputted separately according to the channels.
摘要翻译： 在数据输出装置中，要输出的数据被数字地存储在存储器中，并且在时分多路复用模式下以预定的时间段寻址时被读出，其中地址由计数器提供，其地址的数量 按照每个预定时间段提供的数据对应于所采用的信道数目，并且通过选择电路分别为这些通道分别选择用地址读出的数据，使得它们根据信道被分开地输出。
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公开(公告)号：US20080094096A1
公开(公告)日：2008-04-24
申请号：US11878466
申请日：2007-07-24
IPC分类号： G01R31/26
CPC分类号： G01R31/2894 , G01R31/31721
摘要： In testing a large number of semiconductor devices, semiconductor testing equipment of the present invention is provided with combination determining unit 105 that determines the combination of semiconductor devices to be simultaneously tested among semiconductor devices to be tested, on the basis of one of determination results or measured values in separate testing or manufacturing implemented before and stored in a memory 99, and past determination results or measured values stored in the memory 99 in the present testing.
摘要翻译： 在测试大量半导体器件时，本发明的半导体测试设备提供有组合确定单元105，组合确定单元105基于确定结果之一确定待测试的半导体器件之间要同时测试的半导体器件的组合， 在存储器99之前实施并存储在存储器99中的单独的测试或制造中的测量值以及在本测试中存储在存储器99中的过去的确定结果或测量值。
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公开(公告)号：US07733112B2
公开(公告)日：2010-06-08
申请号：US12173860
申请日：2008-07-16
CPC分类号： G01R31/31725
摘要： A semiconductor testing circuit of the present invention includes a signal line which is connected to a terminal not to be tested and a plurality of terminals to be tested of a semiconductor device; switch circuits for controlling electrical connection/disconnection between the signal line and the terminals to be tested; and a resistor connected to one end of the signal line. With this configuration, in a test on the AC characteristics of an input signal, a test signal generated by an LSI tester can be inputted to the terminals to be tested through the terminal not to be tested and the signal line by turning on the switch circuits.
摘要翻译： 本发明的半导体测试电路包括连接到不被测试的终端的信号线和待测半导体器件的多个终端; 开关电路，用于控制信号线与要测试的端子之间的电连接/断开; 和连接到信号线一端的电阻。 利用这种配置，在对输入信号的AC特性进行测试时，由LSI测试仪产生的测试信号可以通过不经测试的终端和通过接通开关电路的信号线输入到要测试的终端 。
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公开(公告)号：US20090021279A1
公开(公告)日：2009-01-22
申请号：US12173860
申请日：2008-07-16
IPC分类号： G01R31/26
CPC分类号： G01R31/31725
摘要： A semiconductor testing circuit of the present invention includes a signal line which is connected to a terminal not to be tested and a plurality of terminals to be tested of a semiconductor device; switch circuits for controlling electrical connection/disconnection between the signal line and the terminals to be tested; and a resistor connected to one end of the signal line. With this configuration, in a test on the AC characteristics of an input signal, a test signal generated by an LSI tester can be inputted to the terminals to be tested through the terminal not to be tested and the signal line by turning on the switch circuits.
摘要翻译： 本发明的半导体测试电路包括连接到不被测试的终端的信号线和待测半导体器件的多个终端; 开关电路，用于控制信号线与要测试的端子之间的电连接/断开; 和连接到信号线一端的电阻。 利用这种配置，在对输入信号的AC特性进行测试时，由LSI测试仪产生的测试信号可以通过不经测试的终端和通过接通开关电路的信号线输入到要测试的终端 。
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