公开(公告)号：US07307866B2

公开(公告)日：2007-12-11

申请号：US11132196

申请日：2005-05-19

申请人： Kunisato Yamaoka ,  Hiroshige Hirano ,  Yasushi Gohou ,  Shunichi Iwanari ,  Yasuo Murakuki ,  Masahiko Sakagami ,  Tetsuji Nakakuma ,  Takashi Miki

发明人： Kunisato Yamaoka ,  Hiroshige Hirano ,  Yasushi Gohou ,  Shunichi Iwanari ,  Yasuo Murakuki ,  Masahiko Sakagami ,  Tetsuji Nakakuma ,  Takashi Miki

IPC分类号： G11C11/22 ,  G11C11/42 ,  G11C5/14 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C11/22

摘要： A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.

摘要翻译： 本发明的铁电存储器包括：多个正常单元，每个单元包括用于保持数据的第一铁电电容器和连接到第一铁电电容器的第一电极的第一晶体管; 连接到第一晶体管的第一位线; 第一位线预充电电路，其是设置在第一位线和地之间的开关电路; 以及连接到第一晶体管的栅极的字线。 在驱动第一位线预充电电路以放电第一位线的电位之前，字线被去激活以将第一铁电电容器与第一位线断开。

公开(公告)号：US07280406B2

公开(公告)日：2007-10-09

申请号：US11344199

申请日：2006-02-01

申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

IPC分类号： G11C16/06

CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2207/229

摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

摘要翻译： 提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。 当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。 同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。 当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

公开(公告)号：USRE41879E1

公开(公告)日：2010-10-26

申请号：US12155392

申请日：2008-06-03

申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

IPC分类号： G11C16/06

CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2207/229

摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

摘要翻译： 提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。 当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。 同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。 当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

公开(公告)号：US07136313B2

公开(公告)日：2006-11-14

申请号：US11121939

申请日：2005-05-05

申请人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

发明人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/816 ,  G11C11/22 ,  G11C29/789 ,  G11C2029/4402

摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost.A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

摘要翻译： 为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。 半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。 选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

公开(公告)号：US20050265090A1

公开(公告)日：2005-12-01

申请号：US11121939

申请日：2005-05-05

申请人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

发明人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

IPC分类号： G11C11/22 ,  G11C7/00 ,  G11C29/00 ,  G11C29/12

CPC分类号： G11C29/816 ,  G11C11/22 ,  G11C29/789 ,  G11C2029/4402

摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

摘要翻译： 为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。 半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。 选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

公开(公告)号：US20060171246A1

公开(公告)日：2006-08-03

申请号：US11344199

申请日：2006-02-01

申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

IPC分类号： G11C8/00

CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2207/229

摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

摘要翻译： 提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。 当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。 同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。 当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

公开(公告)号：US20050259461A1

公开(公告)日：2005-11-24

申请号：US11132196

申请日：2005-05-19

申请人： Kunisato Yamaoka ,  Hiroshige Hirano ,  Yasushi Gohou ,  Shunichi Iwanari ,  Yasuo Murakuki ,  Masahiko Sakagami ,  Tetsuji Nakakuma ,  Takashi Miki

发明人： Kunisato Yamaoka ,  Hiroshige Hirano ,  Yasushi Gohou ,  Shunichi Iwanari ,  Yasuo Murakuki ,  Masahiko Sakagami ,  Tetsuji Nakakuma ,  Takashi Miki

IPC分类号： G11C11/22 ,  H01L27/10

CPC分类号： G11C11/22

摘要： A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.

摘要翻译： 本发明的铁电存储器包括：多个正常单元，每个单元包括用于保持数据的第一铁电电容器和连接到第一铁电电容器的第一电极的第一晶体管; 连接到第一晶体管的第一位线; 第一位线预充电电路，其是设置在第一位线和地之间的开关电路; 以及连接到第一晶体管的栅极的字线。 在驱动第一位线预充电电路以放电第一位线的电位之前，字线被去激活以将第一铁电电容器与第一位线断开。

公开(公告)号：US07016247B2

公开(公告)日：2006-03-21

申请号：US11023663

申请日：2004-12-29

申请人： Yasuo Murakuki ,  Masahiko Sakagami ,  Shunichi Iwanari

发明人： Yasuo Murakuki ,  Masahiko Sakagami ,  Shunichi Iwanari

IPC分类号： G11C7/00

CPC分类号： G11C17/18 ,  G11C29/785

摘要： A semiconductor memory apparatus including a simple circuit configuration and is capable of randomly accessing fuse data. A fuse cell 30 including a fuse 31 is connected to a pair of bit lines of a memory circuit. The fuse 31 and a fuse data output circuit (which includes a resistor 32 and an inverter 33) are connected to a pair of bit lines BLT and BLB of the memory circuit through a fuse selection switch 34. By allowing a column decoder 12 for selecting a pair of bit lines of the memory cell to also function as a decoder circuit for selecting a fuse, the bit lines of the memory circuit can be used as signal lines for outputting fuse data, whereby the circuit size is reduced and the circuit area is reduced.

摘要翻译： 一种半导体存储装置，包括简单的电路结构，能够随机访问熔丝数据。 包括熔丝31的熔丝单元30连接到存储电路的一对位线。 熔丝31和熔丝数据输出电路（其包括电阻32和反相器33）通过熔丝选择开关34连接到存储电路的一对位线BLT和BLB。 通过允许列解码器12选择存储器单元的一对位线也用作用于选择熔丝的解码器电路，存储电路的位线可以用作用于输出熔丝数据的信号线，由此电路 尺寸减小，电路面积减小。

公开(公告)号：US20050146969A1

公开(公告)日：2005-07-07

申请号：US11023663

申请日：2004-12-29

申请人： Yasuo Murakuki ,  Masahiko Sakagami ,  Shunichi Iwanari

发明人： Yasuo Murakuki ,  Masahiko Sakagami ,  Shunichi Iwanari

IPC分类号： G01R31/28 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C17/18 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C17/18 ,  G11C29/785

摘要： A semiconductor memory apparatus is provided which has a simple circuit configuration and is capable of randomly accessing fuse data. In the semiconductor memory apparatus of the present invention, a fuse cell 30 including a fuse 31 is connected to a pair of bit lines of a memory circuit. The fuse 31 and a fuse data output circuit (which includes a resistor 32 and an inverter 33) are connected to a pair of bit lines BLT and BLB of the memory circuit through a fuse selection switch 34. In the semiconductor memory apparatus of the present invention, by allowing a column decoder 12 for selecting a pair of bit lines of the memory cell to also function as a decoder circuit for selecting a fuse, the bit lines of the memory circuit can be used as signal lines for outputting fuse data, whereby the circuit size is reduced and the circuit area is reduced.

摘要翻译： 提供一种半导体存储装置，其具有简单的电路配置并且能够随机访问熔丝数据。 在本发明的半导体存储装置中，包括熔丝31的熔丝单元30连接到存储电路的一对位线。 熔丝31和熔丝数据输出电路（其包括电阻32和反相器33）通过熔丝选择开关34连接到存储电路的一对位线BLT和BLB。 在本发明的半导体存储装置中，通过允许用于选择存储单元的一对位线的列解码器12也用作用于选择熔丝的解码器电路，存储电路的位线可以用作 用于输出熔丝数据的信号线，由此减小电路尺寸并减小电路面积。

公开(公告)号：US20050078547A1

公开(公告)日：2005-04-14

申请号：US10937441

申请日：2004-09-10

申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Yasuo Murakuki

发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Yasuo Murakuki

IPC分类号： G11C11/22 ,  G11C7/02 ,  G11C7/18 ,  G11C11/34 ,  G11C11/40 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： G11C7/02 ,  G11C7/18 ,  G11C11/22

摘要： A semiconductor memory device having a semiconductor substrate includes a plurality of reference cells 4 and a plurality of bit lines 10. The reference cells 4 are formed in a region near the centerline of a predetermined region of the semiconductor substrate which is perpendicular to the bit lines 10. The bit lines 10 form pairs each composed of two adjacent bit lines. Two bit lines 10 in each pair have a first parallel state and a second parallel state in which positions of the two bit lines are reversed from the first parallel state. Each pair of bit lines 10 has at least one cross section 11 where one of the pair of bit lines 10 crosses the other, to switch between the first parallel state and the second parallel state. The cross section 11 is provided in the predetermined region of the semiconductor substrate such that the length of a bit line 10 in the first parallel state is equal to the length of the bit line 10 in the second parallel state. The semiconductor memory device is reduced in size.

摘要翻译： 具有半导体衬底的半导体存储器件包括多个参考单元4和多个位线10.参考单元4形成在半导体衬底的垂直于位线的预定区域的中心线附近的区域中 位线10形成每对由两个相邻位线组成的对。 每对中的两个位线10具有第一并联状态和第二并行状态，其中两个位线的位置与第一并行状态相反。 每对位线10具有至少一个横截面11，其中一对位线10中的一个与另一个位线交叉，以在第一并行状态和第二平行状态之间切换。 横截面11设置在半导体衬底的预定区域中，使得位于第一并联状态的位线10的长度等于位线10在第二平行状态下的长度。 半导体存储器件的尺寸减小。