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    Modify priority of dataset based on number of times the data set is processed by both a data detector circuit and a data decoder circuit
    3.
    发明授权
    Modify priority of dataset based on number of times the data set is processed by both a data detector circuit and a data decoder circuit 有权
    基于由数据检测器电路和数据解码器电路处理数据集的次数来修改数据集的优先级

    公开(公告)号：US09298369B2

    公开(公告)日：2016-03-29

    申请号：US13766874

    申请日：2013-02-14

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Fan Zhang ,  Jun Xiao ,  Kaitlyn T. Nguyen

    IPC: G06F9/46 ,  G06F3/06

    CPC classification number: G06F3/06 ,  G11B20/10009 ,  G11B20/10268 ,  G11B20/10305 ,  G11B20/10527

    Abstract: Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for quality based scheduling processing of data sets. In some cases, a priority indication associated with a data set is modified based upon one or more factors. As an example, the priority indication may be modified based upon a number of times that a given data set processed through both a data detector circuit and a data decoder circuit.

    Abstract translation: 与用于数据处理的系统和方法相关的系统，电路，设备和/或方法，更具体地涉及用于数据集的基于质量的调度处理的系统和方法。 在一些情况下，基于一个或多个因素修改与数据集相关联的优先指示。 作为示例，可以基于通过数据检测器电路和数据解码器电路来处理的给定数据集的次数来修改优先级指示。

    Systems and methods for data processing using global iteration result reuse
    4.
    发明授权
    Systems and methods for data processing using global iteration result reuse 有权
    使用全局迭代结果重用的数据处理系统和方法

    公开(公告)号：US09274889B2

    公开(公告)日：2016-03-01

    申请号：US13912059

    申请日：2013-06-06

    Applicant: LSI Corporation

    Inventor： Fan Zhang ,  Shu Li ,  Jun Xiao ,  Kaitlyn T. Nguyen

    IPC: G06F11/10 ,  H03M13/11 ,  H03M13/27 ,  H03M13/00 ,  H03M13/29

    CPC classification number: G06F11/1076 ,  H03M13/1111 ,  H03M13/27 ,  H03M13/2948 ,  H03M13/2957 ,  H03M13/6331 ,  H03M13/658 ,  H03M13/6583 ,  H04L2201/06

    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for use of a detector output by a data decoder. As an example, a data processing system is discussed that includes a data detector circuit operable to provide a first detector output and a second detector output, and a combining circuit operable to combine a first input derived from the first detector output with a second input derived from the second detector output to yield a combined detector output. The combined detector output includes a unified data set element generated by combining an element of the first input with a corresponding element of the second input.

    Abstract translation: 本发明涉及用于数据处理的系统和方法，更具体地涉及用于由数据解码器输出的检测器的系统和方法。 作为示例，讨论了包括可操作以提供第一检测器输出和第二检测器输出的数据检测器电路的数据处理系统，以及组合电路，其可操作以将从第一检测器输出导出的第一输入与导出的第二输入 从第二检测器输出产生组合的检测器输出。 组合的检测器输出包括通过将第一输入的元素与第二输入的相应元素组合而产生的统一数据集元素。

    System and Method for Elastic Despreader Memory Management
    5.
    发明申请
    System and Method for Elastic Despreader Memory Management 审中-公开
    弹性解扩器内存管理系统与方法

    公开(公告)号：US20150269097A1

    公开(公告)日：2015-09-24

    申请号：US14230908

    申请日：2014-03-31

    Applicant: LSI Corporation

    Inventor： Ku Hong Jeong ,  Qi Zuo ,  Shaohua Yang ,  Kaitlyn T. Nguyen

    IPC: G06F13/16

    CPC classification number: G06F13/1673 ,  G06F5/12 ,  G06F5/14 ,  H04L49/9005 ,  H04L49/9031 ,  H04L49/9036

    Abstract: The disclosure is directed to a system and method of managing memory resources in a communication channel. According to various embodiments, incoming memory slices associated with a plurality of data sectors are de-interleaved and transferred sequentially through a buffer to a decoder for further processing. To prevent buffer overflow or degraded decoder performance, the memory availability of the buffer is monitored, and transfers are suspended when the memory availability of the buffer is below a threshold buffer availability.

    Abstract translation: 本公开涉及一种管理通信信道中的存储器资源的系统和方法。 根据各种实施例，与多个数据扇区相关联的输入存储器片段被解交织并且顺序地通过缓冲器传送到解码器用于进一步处理。 为了防止缓冲区溢出或解码器性能下降，缓冲区的内存可用性受到监控，当缓冲区的内存可用性低于阈值缓冲区可用性时，传输将被暂停。

    System and method for check-node unit message processing
    6.
    发明授权
    System and method for check-node unit message processing 有权
    用于校验节点单元消息处理的系统和方法

    公开(公告)号：US09244685B2

    公开(公告)日：2016-01-26

    申请号：US13667450

    申请日：2012-11-02

    Applicant: LSI Corporation

    Inventor： Zongwang Li ,  Chung-Li Wang ,  Kaitlyn T. Nguyen ,  Keklik Bayam Alptekin

    IPC: H03M13/00 ,  G06F9/30

    CPC classification number: G06F9/30145 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/616 ,  H03M13/6566

    Abstract: The disclosure is directed to a system and method for storing and processing check-node unit (CNU) messages utilizing random access memory (RAM). A decoder includes a layered array of CNUs configured to receive at least one variable-node unit (VNU) message associated with decoded bits of at least one data segment being operated upon by the decoder. The decoder further includes a CNU message converter configured to permutate at least one initial circulant of the VNU message to generate a converted CNU message having sub-circulants sized for RAM-based processing. The decoder further includes RAM configured to store sub-circulants of the converted CNU message at addressable memory blocks for parallel VNU processing.

    Abstract translation: 本公开涉及一种利用随机存取存储器（RAM）存储和处理校验节点单元（CNU）消息的系统和方法。 解码器包括CNU的分层阵列，其被配置为接收与解码器正在操作的至少一个数据段的解码比特相关联的至少一个可变节点单元（VNU）消息。 解码器还包括CNU消息转换器，其被配置为置换VNU消息的至少一个初始循环，以生成具有基于RAM的处理的子循环的转换的CNU消息。 解码器还包括RAM，其被配置为将转换的CNU消息的子循环存储在可寻址存储器块处以用于并行VNU处理。

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