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1.发明授权Joint transmitter and receiver gain optimization for high-speed serial data systems 有权用于高速串行数据系统的联合发射机和接收机增益优化公开(公告)号：US08848769B2
公开(公告)日：2014-09-30
申请号：US13647502
申请日：2012-10-09
Applicant: LSI Corporation
Inventor： Mohammad Mobin , Vladimir Sindalovsky , Amaresh Malipatil , Thomas F. Gibbons, Jr. , Ye Liu , Lane A. Smith
CPC classification number: H04B1/40 , H04L25/03343 , H04L25/03885
Abstract: Embodiments of the present invention allow for adjustment of transmitter amplitude during joint transmitter (TX) and receiver (RX) equalization. During joint TX and RX adaptation, when the receiver requires a gain update, the receiver gain update is masked above or below a preset range. The RX gain update (instruction) is encoded into a transmitter amplitude update (instruction) transferred through back channel communication. The translation of RX gain to TX amplitude update is performed after the RX gain reaches a specified range. Such masking, encoding and translation reserves a certain amount RX gain range to account for RX gain variation due to process, voltage, and temperature (PVT) changes over time, and also to offer better linear equalization in the receiver over a constrained VGA bandwidth.
Abstract translation: 本发明的实施例允许在联合发射机（TX）和接收机（RX）均衡期间调整发射机幅度。 在联合TX和RX适配期间，当接收机需要增益更新时，接收机增益更新被屏蔽在高于或低于预设范围。 RX增益更新（指令）被编码成通过背信道通信传送的发送机幅度更新（指令）。 在RX增益达到指定范围后，RX增益转换为TX幅度更新。 这种屏蔽，编码和转换保留了一定量的RX增益范围，以解决随着时间的过程，电压和温度（PVT）变化引起的RX增益变化，并且还在受限的VGA带宽上在接收机中提供更好的线性均衡。
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2.发明申请JOINT TRANSMITTER AND RECEIVER GAIN OPTIMIZATION FOR HIGH-SPEED SERIAL DATA SYSTEMS 有权高速串行数据系统的联合发射机和接收机增益优化公开(公告)号：US20140098844A1
公开(公告)日：2014-04-10
申请号：US13647502
申请日：2012-10-09
Applicant: LSI Corporation
Inventor： Mohammad Mobin , Vladimir Sindalovsky , Amaresh Malipatil , Thomas F. Gibbons, JR. , Ye Liu , Lane A. Smith
IPC: H04B1/40
CPC classification number: H04B1/40 , H04L25/03343 , H04L25/03885
Abstract: Embodiments of the present invention allow for adjustment of transmitter amplitude during joint transmitter (TX) and receiver (RX) equalization. During joint TX and RX adaptation, when the receiver requires a gain update, the receiver gain update is masked above or below a preset range. The RX gain update (instruction) is encoded into a transmitter amplitude update (instruction) transferred through back channel communication. The translation of RX gain to TX amplitude update is performed after the RX gain reaches a specified range. Such masking, encoding and translation reserves a certain amount RX gain range to account for RX gain variation due to process, voltage, and temperature (PVT) changes over time, and also to offer better linear equalization in the receiver over a constrained VGA bandwidth.
Abstract translation: 本发明的实施例允许在联合发射机（TX）和接收机（RX）均衡期间调整发射机幅度。 在联合TX和RX适配期间，当接收机需要增益更新时，接收机增益更新被屏蔽在高于或低于预设范围。 RX增益更新（指令）被编码成通过背信道通信传送的发送机幅度更新（指令）。 在RX增益达到指定范围后，RX增益转换为TX幅度更新。 这种屏蔽，编码和转换保留了一定量的RX增益范围，以解决随着时间的过程，电压和温度（PVT）变化引起的RX增益变化，并且还在受限的VGA带宽上在接收机中提供更好的线性均衡。
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公开(公告)号：US09294314B2
公开(公告)日：2016-03-22
申请号：US14228913
申请日：2014-03-28
Applicant: LSI Corporation
Inventor： Mohammad S. Mobin , Pervez M. Aziz , Ye Liu
CPC classification number: H04L25/03057 , H04L7/10 , H04L25/03063 , H04L27/0002 , H04L2025/03636
Abstract: A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the limited equalized received signal. In the linear path, a clock recovery circuit generates a clock signal from the equalized received signal. A delay circuit in the linear path at least partially compensates for propagation delay in the limiter. Having the clock recovery occur in other than the nonlinear path, a low jitter clock is generated. The limiter enhances the vertical opening of the data eye by increasing the rise and fall times of the limited signal, providing more noise margin for the slicer to operate with and a greater timing margin in which to sample the sliced data.
Abstract translation: 一种具有线性路径和非线性路径的接收机的通信系统。 随着接收机接收数据信号，它自适应地均衡接收信号，并且使用可饱和放大器限幅器等对非线性路径中的均衡信号进行幅度限幅。 限幅器从有限的均衡接收信号中提取数据。 在线性路径中，时钟恢复电路从均衡的接收信号产生时钟信号。 线性路径中的延迟电路至少部分地补偿限幅器中的传播延迟。 在非线性路径之外发生时钟恢复，产生低抖动时钟。 限幅器通过增加受限信号的上升和下降时间来增强数据眼睛的垂直开度，为切片机操作提供更多的噪声容限，并在其中对切片数据进行采样提供更大的定时余量。
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Patent Agency Ranking
公开(公告)号：US20150249555A1
公开(公告)日：2015-09-03
申请号：US14244474
申请日：2014-04-03
Applicant: LSI Corporation
Inventor： Mohammad S. Mobin , Weiwei Mao , Chintan M. Desai , Freeman Y. Zhong , Ye Liu
CPC classification number: H04L25/03057 , H04L25/03885 , H04L25/06
Abstract: In described embodiments, process, voltage, temperature (PVT) compensation in a serializer/deserializer (SerDes) device employs a closed loop adaptation compensation that is incorporated into the SerDes receiver adaptation process. A detection method, where the adapted decision feedback equalizer (DFE) target level (e.g., tap H0) is monitored, employs this DFE target level when implementing a closed loop variable gain amplifier adaptation. The DFE target level in conjunction with the VGA level is used to control the PVT setting to maintain target SerDes data path gain by detecting aPVT corner condition. The detected PVT corner condition is employed to generate a control signal to further adjust the LEQ and DFE data path differential pair gain as required by the PVT condition.
Abstract translation: 在所描述的实施例中，串行器/解串器（SerDes）器件中的处理，电压，温度（PVT）补偿采用并入SerDes接收器适配过程的闭环适配补偿。 在实施闭环可变增益放大器适配时，其中监视适应的判决反馈均衡器（DFE）目标电平（例如，抽头H0）的检测方法采用该DFE目标电平。 DFE目标水平与VGA电平一起用于控制PVT设置，以通过检测一个电压转角条件来维持目标SerDes数据通路增益。 检测到的PVT拐角条件用于产生控制信号，以进一步调整根据PVT条件所要求的LEQ和DFE数据路径差分对增益。
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公开(公告)号：US09325537B2
公开(公告)日：2016-04-26
申请号：US14244474
申请日：2014-04-03
Applicant: LSI Corporation
Inventor： Mohammad S. Mobin , Weiwei Mao , Chintan M. Desai , Freeman Y. Zhong , Ye Liu
CPC classification number: H04L25/03057 , H04L25/03885 , H04L25/06
Abstract: In described embodiments, process, voltage, temperature (PVT) compensation in a serializer/deserializer (SerDes) device employs a closed loop adaptation compensation that is incorporated into the SerDes receiver adaptation process. A detection method, where the adapted decision feedback equalizer (DFE) target level (e.g., tap H0) is monitored, employs this DFE target level when implementing a closed loop variable gain amplifier adaptation. The DFE target level in conjunction with the VGA level is used to control the PVT setting to maintain target SerDes data path gain by detecting aPVT corner condition. The detected PVT corner condition is employed to generate a control signal to further adjust the LEQ and DFE data path differential pair gain as required by the PVT condition.
Abstract translation: 在所描述的实施例中，串行器/解串器（SerDes）器件中的处理，电压，温度（PVT）补偿采用并入SerDes接收器适配过程的闭环适配补偿。 在实施闭环可变增益放大器适配时，其中监视适应的判决反馈均衡器（DFE）目标电平（例如，抽头H0）的检测方法采用该DFE目标电平。 DFE目标水平与VGA电平一起用于控制PVT设置，以通过检测一个电压转角条件来维持目标SerDes数据通路增益。 检测到的PVT拐角条件用于产生控制信号，以进一步调整根据PVT条件所要求的LEQ和DFE数据路径差分对增益。
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公开(公告)号：US20150263848A1
公开(公告)日：2015-09-17
申请号：US14257315
申请日：2014-04-21
Applicant: LSI Corporation
Inventor： Mohammad S. Mobin , Weiwei Mao , Chintan M. Desai , Ye Liu
CPC classification number: H03L7/0807 , H04L7/0004 , H04L7/033
Abstract: Described embodiments provide for, in a clock and data recovery (CDR) circuit, detection of loss of acquisition and CDR restarting with corrective integral accumulator register seeding and gearshift restarting. In described embodiments, a mechanism is employed to cause faster loss of lock condition if the CDR circuit directed on an incorrect acquisition trajectory, actual loss of CDR lock is then detected, and CDR acquisition is recovered with corrective integral accumulator seeding.
Abstract translation: 描述的实施例在时钟和数据恢复（CDR）电路中提供使用校正积分累加器寄存器种子和换档重启的检测丢失采集和CDR重新启动。 在所描述的实施例中，如果针对不正确的采集轨迹的CDR电路，然后检测到CDR锁的实际丢失，并且通过校正积分累加器种子恢复CDR采集，则采用机制来引起更快的锁定状态丢失。
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7.发明授权Pre and post-acquisition tap quantization adjustment in decision feedback equalizer 有权决策反馈均衡器中的前采集和采集后抽头量化调整公开(公告)号：US08867602B1
公开(公告)日：2014-10-21
申请号：US14011236
申请日：2013-08-27
Applicant: LSI Corporation
Inventor： Mohammad S. Mobin , Weiwei Mao , Ye Liu , Brett D. Hardy , Lane A. Smith
CPC classification number: H04L25/03885 , H04L25/03057
Abstract: A tap coefficient control circuit and a method for controlling a tap coefficient for a decision feedback equalizer are disclosed. The method includes adjusting a correction voltage applied to the tap coefficient based on a first tap quantization and detecting a decision feedback equalizer tap convergence. After the decision feedback equalizer tap convergence is detected, the method adjusts the correction voltage applied to the tap coefficient based on a second tap quantization, wherein the second tap quantization is different from the first tap quantization.
Abstract translation: 公开了抽头系数控制电路和用于控制用于判决反馈均衡器的抽头系数的方法。 该方法包括基于第一抽头量化来调整施加到抽头系数的校正电压，并且检测判决反馈均衡器抽头收敛。 在检测到判定反馈均衡器抽头收敛之后，该方法基于第二抽头量化调整施加到抽头系数的校正电压，其中第二抽头量化与第一抽头量化不同。
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公开(公告)号：US20140211839A1
公开(公告)日：2014-07-31
申请号：US14228913
申请日：2014-03-28
Applicant: LSI Corporation
Inventor： Mohammad S. Mobin , Pervez M. Aziz , Ye Liu
IPC: H04L25/03
CPC classification number: H04L25/03057 , H04L7/10 , H04L25/03063 , H04L27/0002 , H04L2025/03636
Abstract: A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the limited equalized received signal. In the linear path, a clock recovery circuit generates a clock signal from the equalized received signal. A delay circuit in the linear path at least partially compensates for propagation delay in the limiter. Having the clock recovery occur in other than the nonlinear path, a low jitter clock is generated. The limiter enhances the vertical opening of the data eye by increasing the rise and fall times of the limited signal, providing more noise margin for the slicer to operate with and a greater timing margin in which to sample the sliced data.
Abstract translation: 一种具有线性路径和非线性路径的接收机的通信系统。 随着接收机接收数据信号，它自适应地均衡接收信号，并且使用可饱和放大器限幅器等对非线性路径中的均衡信号进行幅度限幅。 限幅器从有限的均衡接收信号中提取数据。 在线性路径中，时钟恢复电路从均衡的接收信号产生时钟信号。 线性路径中的延迟电路至少部分地补偿限幅器中的传播延迟。 在非线性路径之外发生时钟恢复，产生低抖动时钟。 限幅器通过增加受限信号的上升和下降时间来增强数据眼睛的垂直开度，为切片机操作提供更多的噪声容限以及更大的定时裕度来采样分片数据。
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