-
公开(公告)号：US06941440B2
公开(公告)日：2005-09-06
申请号：US10439297
申请日：2003-05-15
申请人： Laurent R. Moll , James D. Kelly , Manu Gulati , Koray Oner , Joseph B. Rowlands
发明人： Laurent R. Moll , James D. Kelly , Manu Gulati , Koray Oner , Joseph B. Rowlands
CPC分类号： G06F13/1684
摘要： A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.
-
公开(公告)号：US06941406B2
公开(公告)日：2005-09-06
申请号：US10861624
申请日：2004-06-04
申请人： Barton J. Sano , Joseph B. Rowlands , James B. Keller , Laurent R. Moll , Koray Oner , Manu Gulati
发明人： Barton J. Sano , Joseph B. Rowlands , James B. Keller , Laurent R. Moll , Koray Oner , Manu Gulati
IPC分类号： G06F12/08 , G06F13/00 , G06F13/14 , G06F13/28 , G06F13/36 , G06F15/167 , H04L12/56 , H04Q11/00
CPC分类号： H04L49/901 , G06F12/0813 , G06F13/28 , H04L49/103 , H04L49/3009 , H04L49/90 , H04L49/9063 , H04L49/9073
摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.
-
3.发明授权System having interfaces and switch that separates coherent and packet traffic 有权具有分离相干和分组业务的接口和交换机的系统公开(公告)号：US06748479B2
公开(公告)日：2004-06-08
申请号：US10270029
申请日：2002-10-11
申请人： Barton J. Sano , Joseph B. Rowlands , James B. Keller , Laurent R. Moll , Koray Oner , Manu Gulati
发明人： Barton J. Sano , Joseph B. Rowlands , James B. Keller , Laurent R. Moll , Koray Oner , Manu Gulati
IPC分类号： G06F1300
CPC分类号： H04L49/901 , G06F12/0813 , G06F13/28 , H04L49/103 , H04L49/3009 , H04L49/90 , H04L49/9063 , H04L49/9073
摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.
摘要翻译： 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些相关命令来在互连上发起相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。
-
4.发明授权System having two or more packet interfaces, a switch, and a shared packet DMA circuit 有权具有两个或多个分组接口的系统，交换机和共享分组DMA电路公开(公告)号：US06912602B2
公开(公告)日：2005-06-28
申请号：US10269666
申请日：2002-10-11
申请人： Barton J. Sano , Koray Oner , Laurent R. Moll , Manu Gulati
发明人： Barton J. Sano , Koray Oner , Laurent R. Moll , Manu Gulati
CPC分类号： H04L49/10 , H04L49/602
摘要： An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.
摘要翻译： 一种装置包括第一接口电路，第二接口电路，用于配置为与存储器接口的存储器控制器和分组DMA电路。 第一接口电路被配置为耦合到用于接收和发送分组数据的第一接口。 类似地，第二接口电路被配置为耦合到用于接收和发送分组数据的第二接口。 分组DMA电路被耦合以从第一接口电路接收第一分组，并从第二接口电路接收第二分组。 分组DMA电路被配置为以写入命令将第一分组和第二分组发送到存储器控制器以写入存储器。 在一些实施例中，开关耦合到第一接口电路，第二接口电路和分组DMA电路。
-
5.发明授权Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems 失效使用分组，相干和非相干流量混合的系统来优化系统之间的传输公开(公告)号：US07424561B2
公开(公告)日：2008-09-09
申请号：US11717511
申请日：2007-03-13
CPC分类号： G06F13/4022
摘要： An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.
摘要翻译： 装置可以包括第一系统和第二系统。 第一系统包括第一多个接口电路，并且第一多个接口电路中的每一个配置成耦合到单独的接口。 第二系统包括第二多个接口电路，并且第二多个接口电路中的每一个被配置为耦合到单独的接口。 第一多个接口电路的第一接口电路和第二多个接口电路的第二接口电路耦合到第一接口。 第一接口电路和第二接口电路均被配置为在第一接口上传送分组，相关命令和非相干命令。
-
6.发明授权Transparent data format within host device supporting differing transaction types 有权支持不同事务类型的主机设备内的透明数据格式公开(公告)号：US07313146B2
公开(公告)日：2007-12-25
申请号：US10684989
申请日：2003-10-14
申请人： Laurent R. Moll , Manu Gulati , Joseph B. Rowlands
发明人： Laurent R. Moll , Manu Gulati , Joseph B. Rowlands
IPC分类号： H04L12/56
摘要： A system for servicing packet data transactions and input/output transactions includes an input port, an output port, a node controller, a packet manager, and a switching module. The input port is receives communications from a communicatively coupled processing device that include packet data transactions and input/output transactions. The output port transmits communications to a communicatively coupled processing device that include packet data transactions and input/output transactions. The node controller communicatively couples to a system bus of the processing device and services input/output transactions. The packet manager communicatively couples to the system bus of the processing device and services packet data transactions. A switching module communicatively couples to the input port, the output port, the node controller, and the packet manager and services the exchange of transaction cells among the input port, the output port, the node controller, and the packet manager. Each transaction cell has a control tag and data and carrying all or a portion of a packet data transaction or an input/output transaction.
摘要翻译： 用于对分组数据事务和输入/输出事务进行服务的系统包括输入端口，输出端口，节点控制器，分组管理器和交换模块。 输入端口从包括分组数据事务和输入/输出事务的通信耦合的处理设备接收通信。 输出端口将通信发送到包括分组数据事务和输入/输出事务的通信耦合处理设备。 节点控制器通信地耦合到处理设备的系统总线并且服务输入/输出事务。 分组管理器通信地耦合到处理设备的系统总线和服务分组数据事务。 交换模块通信地耦合到输入端口，输出端口，节点控制器和分组管理器，并且为输入端口，输出端口，节点控制器和分组管理器之间的事务单元的交换提供服务。 每个事务单元具有控制标签和数据，并且携带分组数据事务或输入/输出事务的全部或一部分。
-
7.发明授权Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems 有权使用分组，相干和非相干流量混合的系统来优化系统之间的传输公开(公告)号：US07206879B2
公开(公告)日：2007-04-17
申请号：US10269922
申请日：2002-10-11
CPC分类号： G06F13/4022
摘要： An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.
摘要翻译： 装置可以包括第一系统和第二系统。 第一系统包括第一多个接口电路，并且第一多个接口电路中的每一个被配置为耦合到单独的接口。 第二系统包括第二多个接口电路，并且第二多个接口电路中的每一个被配置为耦合到单独的接口。 第一多个接口电路的第一接口电路和第二多个接口电路的第二接口电路耦合到第一接口。 第一接口电路和第二接口电路均被配置为在第一接口上传送分组，相关命令和非相干命令。
-
8.发明授权Apparatus and method to receive and align incoming data including SPI data in a buffer to expand data width by utilizing a single read port and single write port memory device 失效用于接收和对准输入数据的装置和方法，包括缓冲器中的SPI数据，以通过使用单个读取端口和单个写入端口存储器件来扩展数据宽度公开(公告)号：US07551645B2
公开(公告)日：2009-06-23
申请号：US10685231
申请日：2003-10-14
申请人： Manu Gulati , Laurent R. Moll
发明人： Manu Gulati , Laurent R. Moll
IPC分类号： H04J3/24
CPC分类号： H04L49/552 , H04L49/3072
摘要： A re-assembly buffer for use in interim storage of aligned data and to reassemble data output onto a wider internal data path, in which the width of the data path is determined to have sufficient bandwidth to account for frequency scaling of received data rate to frequency of the data path and fragmentation of data for alignment onto the data path. The buffer may be is arranged into arrays using single read port, single write port memory devices.
摘要翻译： 一种重组缓冲器，用于对准数据的临时存储并将数据输出重新组合到更宽的内部数据路径上，其中数据路径的宽度被确定为具有足够的带宽以将接收到的数据速率频率缩放到频率 的数据路径和数据碎片，以便对准数据路径。 可以使用单个读取端口，单个写入端口存储器件将缓冲器布置成阵列。
-
公开(公告)号：US07490187B2
公开(公告)日：2009-02-10
申请号：US10742060
申请日：2003-12-20
申请人： Laurent R. Moll , Manu Gulati
发明人： Laurent R. Moll , Manu Gulati
IPC分类号： G06F13/20
CPC分类号： G06F13/423
摘要： A dual mode digital interface supports the HyperTransport Standard and at least one other interface standard. The dual mode digital interface includes a physical interface, a plurality of data line amplifiers, a clock line amplifier, a plurality of data line deskew/sampling blocks, a data group deskew module, and an enablement control module. The plurality of data line deskew/sampling blocks deskew and sample incoming data on respective data lines based upon a clock signal to produce deskewed data. The data group deskew module receives deskewed data from each of the plurality of data line deskew/sampling blocks and removes inter data line skew from the deskewed data to produce received data. The plurality of data line deskew/sampling blocks and the data group deskew module may be set based upon a training sequence received from a link partner. The training sequence may received during startup or reset, immediately after startup or reset completes, or may be received periodically during training intervals.
摘要翻译： 双模式数字接口支持超传输标准和至少一种其他接口标准。 双模数字接口包括物理接口，多个数据线放大器，时钟线放大器，多个数据线去歪斜/采样块，数据组歪斜模块和启用控制模块。 多个数据线去歪斜/采样块基于时钟信号在相应数据线上进行去歪斜和采样输入数据以产生偏斜数据。 数据组去偏移模块从多个数据线去歪斜/采样块中的每一个接收偏斜数据，并从数据交换数据中移出数据线偏移以产生接收到的数据。 可以基于从链路伙伴接收的训练序列来设置多个数据线去歪斜/采样块和数据组歪斜模块。 训练序列可以在启动或复位期间立即在启动或复位完成之后接收，或者可以在训练间隔期间周期性接收。
-
10.发明授权Apparatus and method to receive and decode incoming data and to handle repeated simultaneous small fragments 有权接收和解码输入数据并处理重复的同时小碎片的装置和方法公开(公告)号：US07319702B2
公开(公告)日：2008-01-15
申请号：US10684998
申请日：2003-10-14
申请人： Laurent R. Moll , Manu Gulati
发明人： Laurent R. Moll , Manu Gulati
IPC分类号： H04L12/56
CPC分类号： G06F13/4018
摘要： A data aligner aligns a data segment having a granularity of less than a width of an internal data path. The data aligner aligns a fragment of data for alignment with a current segment or delay the fragment to combine with a next segment for alignment of data. A buffer receives the aligned data from the data aligner for interim storage and subsequent output onto an internal data path.
摘要翻译： 数据对齐器对齐具有小于内部数据路径的宽度的粒度的数据段。 数据对齐器对齐数据片段以与当前片段对齐，或将片段延迟与下一片段组合，以便对齐数据。 缓冲器从数据对准器接收对准的数据，用于临时存储和后续输出到内部数据路径。
-
-
-
-
-
-
-
-
-
搜索结果
35 条记录 (耗时 0.031 秒)
