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公开(公告)号：US06941440B2
公开(公告)日：2005-09-06
申请号：US10439297
申请日：2003-05-15
申请人： Laurent R. Moll , James D. Kelly , Manu Gulati , Koray Oner , Joseph B. Rowlands
发明人： Laurent R. Moll , James D. Kelly , Manu Gulati , Koray Oner , Joseph B. Rowlands
CPC分类号： G06F13/1684
摘要： A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.
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公开(公告)号：US06941406B2
公开(公告)日：2005-09-06
申请号：US10861624
申请日：2004-06-04
申请人： Barton J. Sano , Joseph B. Rowlands , James B. Keller , Laurent R. Moll , Koray Oner , Manu Gulati
发明人： Barton J. Sano , Joseph B. Rowlands , James B. Keller , Laurent R. Moll , Koray Oner , Manu Gulati
IPC分类号： G06F12/08 , G06F13/00 , G06F13/14 , G06F13/28 , G06F13/36 , G06F15/167 , H04L12/56 , H04Q11/00
CPC分类号： H04L49/901 , G06F12/0813 , G06F13/28 , H04L49/103 , H04L49/3009 , H04L49/90 , H04L49/9063 , H04L49/9073
摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.
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3.发明授权System having interfaces and switch that separates coherent and packet traffic 有权具有分离相干和分组业务的接口和交换机的系统公开(公告)号：US06748479B2
公开(公告)日：2004-06-08
申请号：US10270029
申请日：2002-10-11
申请人： Barton J. Sano , Joseph B. Rowlands , James B. Keller , Laurent R. Moll , Koray Oner , Manu Gulati
发明人： Barton J. Sano , Joseph B. Rowlands , James B. Keller , Laurent R. Moll , Koray Oner , Manu Gulati
IPC分类号： G06F1300
CPC分类号： H04L49/901 , G06F12/0813 , G06F13/28 , H04L49/103 , H04L49/3009 , H04L49/90 , H04L49/9063 , H04L49/9073
摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.
摘要翻译： 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些相关命令来在互连上发起相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。
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4.发明授权Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems 失效使用分组，相干和非相干流量混合的系统来优化系统之间的传输公开(公告)号：US07424561B2
公开(公告)日：2008-09-09
申请号：US11717511
申请日：2007-03-13
CPC分类号： G06F13/4022
摘要： An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.
摘要翻译： 装置可以包括第一系统和第二系统。 第一系统包括第一多个接口电路，并且第一多个接口电路中的每一个配置成耦合到单独的接口。 第二系统包括第二多个接口电路，并且第二多个接口电路中的每一个被配置为耦合到单独的接口。 第一多个接口电路的第一接口电路和第二多个接口电路的第二接口电路耦合到第一接口。 第一接口电路和第二接口电路均被配置为在第一接口上传送分组，相关命令和非相干命令。
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5.发明授权Transparent data format within host device supporting differing transaction types 有权支持不同事务类型的主机设备内的透明数据格式公开(公告)号：US07313146B2
公开(公告)日：2007-12-25
申请号：US10684989
申请日：2003-10-14
申请人： Laurent R. Moll , Manu Gulati , Joseph B. Rowlands
发明人： Laurent R. Moll , Manu Gulati , Joseph B. Rowlands
IPC分类号： H04L12/56
摘要： A system for servicing packet data transactions and input/output transactions includes an input port, an output port, a node controller, a packet manager, and a switching module. The input port is receives communications from a communicatively coupled processing device that include packet data transactions and input/output transactions. The output port transmits communications to a communicatively coupled processing device that include packet data transactions and input/output transactions. The node controller communicatively couples to a system bus of the processing device and services input/output transactions. The packet manager communicatively couples to the system bus of the processing device and services packet data transactions. A switching module communicatively couples to the input port, the output port, the node controller, and the packet manager and services the exchange of transaction cells among the input port, the output port, the node controller, and the packet manager. Each transaction cell has a control tag and data and carrying all or a portion of a packet data transaction or an input/output transaction.
摘要翻译： 用于对分组数据事务和输入/输出事务进行服务的系统包括输入端口，输出端口，节点控制器，分组管理器和交换模块。 输入端口从包括分组数据事务和输入/输出事务的通信耦合的处理设备接收通信。 输出端口将通信发送到包括分组数据事务和输入/输出事务的通信耦合处理设备。 节点控制器通信地耦合到处理设备的系统总线并且服务输入/输出事务。 分组管理器通信地耦合到处理设备的系统总线和服务分组数据事务。 交换模块通信地耦合到输入端口，输出端口，节点控制器和分组管理器，并且为输入端口，输出端口，节点控制器和分组管理器之间的事务单元的交换提供服务。 每个事务单元具有控制标签和数据，并且携带分组数据事务或输入/输出事务的全部或一部分。
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6.发明授权Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems 有权使用分组，相干和非相干流量混合的系统来优化系统之间的传输公开(公告)号：US07206879B2
公开(公告)日：2007-04-17
申请号：US10269922
申请日：2002-10-11
CPC分类号： G06F13/4022
摘要： An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.
摘要翻译： 装置可以包括第一系统和第二系统。 第一系统包括第一多个接口电路，并且第一多个接口电路中的每一个被配置为耦合到单独的接口。 第二系统包括第二多个接口电路，并且第二多个接口电路中的每一个被配置为耦合到单独的接口。 第一多个接口电路的第一接口电路和第二多个接口电路的第二接口电路耦合到第一接口。 第一接口电路和第二接口电路均被配置为在第一接口上传送分组，相关命令和非相干命令。
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公开(公告)号：US06948035B2
公开(公告)日：2005-09-20
申请号：US10414363
申请日：2003-04-15
申请人： Joseph B. Rowlands , Koray Oner
发明人： Joseph B. Rowlands , Koray Oner
CPC分类号： G06F13/4027 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F12/082 , G06F2212/2542
摘要： A node comprises an interconnect, circuitry coupled to the interconnect and configured to initiate a transaction on the interconnect, and a control circuit coupled to provide a response to the transaction on the interconnect. The transaction addresses a block, and the response is indicative of a state of the block in one or more other nodes. The control circuit is configured to cause the transaction to become globally visible to the one or more other nodes dependent on the state in the one or more nodes. Using one or more communication lines separate from lines used to initiate transactions, the control circuit is configured to transmit an indication of the transaction on the interconnect responsive to the transaction becoming globally visible. A transfer of data on the interconnect for the transaction is delayed, responsive to the response from the control circuit, until the indication is transmitted by the control circuit.
摘要翻译： 节点包括互连，耦合到互连并被配置为在互连上启动事务的电路，以及耦合以提供对互连上的事务的响应的控制电路。 事务处理块，并且该响应指示在一个或多个其他节点中的块的状态。 控制电路被配置为使得事务对于一个或多个依赖于一个或多个节点中的状态的其他节点变得全局可见。 使用与用于发起事务的线分开的一个或多个通信线路，控制电路被配置为响应于事务成为全局可见而在互连上发送交易的指示。 响应于来自控制电路的响应，交易的互连上的数据传输被延迟，直到控制电路发送指示。
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公开(公告)号：US07934054B1
公开(公告)日：2011-04-26
申请号：US11751973
申请日：2007-05-22
IPC分类号： G06F12/00
CPC分类号： G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F12/0862 , G06F12/0891 , G06F12/0897 , G06F13/1694 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： A re-fetching cache memory improves efficiency of a system, for example by advantageously sharing the cache memory and/or by increasing performance. When some or all of the cache memory is temporarily used for another purpose, some or all of a data portion of the cache memory is flushed, and some or all of a tag portion is saved in an archive. In some embodiments, some or all of the tag portion operates “in-place” as the archive, and in further embodiments, is placed in a reduced-power mode. When the temporary use completes, optionally and/or selectively, at least some of the tag portion is repopulated from the archive, and the data portion is re-fetched according to the repopulated tag portion. According to various embodiments, processor access to the cache is enabled during one or more of: the saving; the repopulating; and the re-fetching.
摘要翻译： 重新获取高速缓冲存储器提高了系统的效率，例如有利地共享高速缓冲存储器和/或通过提高性能。 当部分或全部缓存存储器临时用于另一目的时，高速缓冲存储器的数据部分的一些或全部被刷新，并且一部分或全部标签部分被保存在存档中。 在一些实施例中，标签部分的一些或全部作为归档操作“就地”，并且在另外的实施例中，被放置在降低功率模式中。 当暂时使用完成时，可选地和/或选择性地，从归档重新填充标签部分的至少一些，并且根据重新填充的标签部分重新获取数据部分。 根据各种实施例，在以下的一个或多个中启用对高速缓存的处理器访问：保存; 重新填补 并重新获取。
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公开(公告)号：US07873788B1
公开(公告)日：2011-01-18
申请号：US11751985
申请日：2007-05-22
IPC分类号： G06F12/00
CPC分类号： G06F12/0891 , G06F12/0815 , G06F12/0862 , G06F2212/1028 , G11C7/20 , Y02D10/13
摘要： A re-fetching cache memory improves efficiency of a processor, for example by reducing power consumption and/or by advantageously sharing the cache memory. When the cache memory is disabled or temporarily used for another purpose, a data portion of the cache memory is flushed, and some or all of a tag portion is saved in an archive. In some embodiments, the tag portion operates “in-place” as the archive, and in further embodiments, is placed in a reduced-power mode. When the cache memory is re-enabled or when the temporary use completes, optionally and/or selectively, the tag portion is repopulated from some or all of the archive, and the data portion is re-fetched according to the repopulated tag portion. The re-fetching is optionally performed in a cache coherent fashion. According to various embodiments, processor access to the cache is enabled during one or more of: the saving; the repopulating; and the re-fetching.
摘要翻译： 重新获取高速缓冲存储器可提高处理器的效率，例如通过降低功耗和/或有利地共享高速缓冲存储器。 当高速缓冲存储器被禁用或临时用于另一目的时，高速缓冲存储器的数据部分被刷新，并且标签部分中的一些或全部被保存在归档中。 在一些实施例中，标签部分作为归档操作“就地”，并且在另外的实施例中，被放置在降低功率模式中。 当高速缓冲存储器被重新启用或临时使用完成时，可选地和/或选择性地，标签部分从档案的一些或全部重新填充，并且根据重新填充的标签部分重新获取数据部分。 重新获取可选地以缓存一致的方式执行。 根据各种实施例，在以下的一个或多个中启用对高速缓存的处理器访问：保存; 重新填补 并重新获取。
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公开(公告)号：US07647452B1
公开(公告)日：2010-01-12
申请号：US11751949
申请日：2007-05-22
IPC分类号： G06F12/00
CPC分类号： G11C7/20 , G06F12/0802 , G06F12/0804 , G06F12/0864 , G06F12/0888 , G06F12/0891 , G06F2212/1021 , G06F2212/1028 , G06F2212/2515 , G11C8/14 , G11C11/413 , G11C2207/2245 , Y02D10/13
摘要： A re-fetching cache memory improves efficiency of a processor, for example by reducing power consumption and/or increasing performance. When the cache memory is disabled or temporarily used for another purpose, a data portion of the cache memory is flushed, and a tag portion is saved in an archive. In some embodiments, the tag portion operates “in-place” as the archive, and in further embodiments, is placed in a reduced-power mode. In some embodiments, less than the full tag portion is archived. When the cache memory is re-enabled or when the temporary use completes, optionally and/or selectively, the tag portion is repopulated from the archive, and the data portion is re-fetched according to the repopulated tag portion. In some embodiments, less than the full archive is restored. According to various embodiments, processor access to the cache is enabled during one or more of: the saving; the repopulating; and the re-fetching.
摘要翻译： 重新获取高速缓冲存储器可以提高处理器的效率，例如降低功耗和/或提高性能。 当缓存存储器被禁用或暂时用于另一目的时，高速缓冲存储器的数据部分被刷新，并且标签部分被保存在存档中。 在一些实施例中，标签部分作为归档操作“就地”，并且在另外的实施例中，被放置在降低功率模式中。 在一些实施例中，小于完整标签部分被归档。 当高速缓冲存储器被重新启用或暂时使用完成时，可选地和/或选择性地，标签部分从归档重新填充，并且数据部分根据重新填充的标签部分重新获取。 在一些实施例中，恢复小于完整归档。 根据各种实施例，在以下的一个或多个中启用对高速缓存的处理器访问：保存; 重新填补 并重新获取。
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