摘要:
A re-assembly buffer for use in interim storage of aligned data and to reassemble data output onto a wider internal data path, in which the width of the data path is determined to have sufficient bandwidth to account for frequency scaling of received data rate to frequency of the data path and fragmentation of data for alignment onto the data path. The buffer may be is arranged into arrays using single read port, single write port memory devices.
摘要:
A dual mode digital interface supports the HyperTransport Standard and at least one other interface standard. The dual mode digital interface includes a physical interface, a plurality of data line amplifiers, a clock line amplifier, a plurality of data line deskew/sampling blocks, a data group deskew module, and an enablement control module. The plurality of data line deskew/sampling blocks deskew and sample incoming data on respective data lines based upon a clock signal to produce deskewed data. The data group deskew module receives deskewed data from each of the plurality of data line deskew/sampling blocks and removes inter data line skew from the deskewed data to produce received data. The plurality of data line deskew/sampling blocks and the data group deskew module may be set based upon a training sequence received from a link partner. The training sequence may received during startup or reset, immediately after startup or reset completes, or may be received periodically during training intervals.
摘要:
A data aligner aligns a data segment having a granularity of less than a width of an internal data path. The data aligner aligns a fragment of data for alignment with a current segment or delay the fragment to combine with a next segment for alignment of data. A buffer receives the aligned data from the data aligner for interim storage and subsequent output onto an internal data path.
摘要:
A dual mode digital interface supports the HyperTransport Standard and at least one other interface standard. The dual mode digital interface includes a plurality of data line deskew/sampling blocks, a data group deskew module, and an enablement control module. The plurality of data line deskew/sampling blocks deskew and sample incoming data on respective data lines based upon a clock signal to produce deskewed data. The data group deskew module receives deskewed data from each of the plurality of data line deskew/sampling blocks and removes inter-data line skew from the deskewed data to produce received data. The plurality of data line deskew/sampling blocks and the data group deskew module can be configured in a first mode when supporting an aspect of the HyperTransport Standard and configured in a second mode when supporting the at least one other interface standard. In the alternative, a plurality of data line deskew/sampling blocks and the data group deskew module may be set based upon a training sequence received from a link partner.
摘要:
An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.
摘要:
A dual mode digital interface supports the HyperTransport Standard and at least one other interface standard. The dual mode digital interface includes a plurality of data line deskew/sampling blocks, a data group deskew module, and an enablement control module. The plurality of data line deskew/sampling blocks deskew and sample incoming data on respective data lines based upon a clock signal to produce deskewed data. The data group deskew module receives deskewed data from each of the plurality of data line deskew/sampling blocks and removes inter-data line skew from the deskewed data to produce received data. The plurality of data line deskew/sampling blocks and the data group deskew module can be configured in a first mode when supporting an aspect of the HyperTransport Standard and configured in a second mode when supporting the at least one other interface standard. In the alternative, a plurality of data line deskew/sampling blocks and the data group deskew module may be set based upon a training sequence received from a link partner.
摘要:
An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.
摘要:
An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.
摘要:
A method for receiving data from a plurality of virtual channels begins by storing a stream of data as a plurality of data segments, wherein the stream of data includes multiplexed data fragments from at least one of the plurality of virtual channels, and wherein a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The method continues by decoding at least one of the plurality of data segments in accordance with one of a plurality of data transmission protocols to produce at least one decoded data segment. The method continues by storing the at least one decoded data segment, in a generic format, to reassemble at least a portion of a packet provided by the at least one of the plurality of virtual channels. The method continues by routing the at least one decoded data segment as at least part of the reassembled packet to one of a plurality of destinations in accordance with the at least one of the plurality of virtual channels.
摘要:
An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.