公开(公告)号：US10018970B2

公开(公告)日：2018-07-10

申请号：US15244132

申请日：2016-08-23

Applicant: MEDIATEK Inc.

Inventor： Yun-Chen Chuang ,  Ang-Sheng Lin

IPC: H03L7/06 ,  G04F10/00 ,  H03L7/085 ,  H03L7/16

CPC classification number: G04F10/005 ,  H03L7/085 ,  H03L7/16 ,  H03L2207/50

Abstract: A time-to-digital system and associated frequency synthesizer are provided. The time-to-digital system receives a reference clock and a variable clock. The time-to-digital system includes a supplement circuit and a time-to-digital converter (TDC). The supplement circuit generates a delayed reference clock signal and at least one pulse of a variable clock ahead of a transition of the delayed reference clock signal. The delayed reference clock signal is generated according to a delay control signal and the reference clock signal. The delay control signal is determined in response to transitions of the variable clock, and frequency of the variable clock is significantly higher than frequency of the reference clock signal. Being coupled to the supplement circuit, the TDC receives the delayed reference clock signal and the at least one pulse of the variable clock and accordingly produces a TDC signal.

公开(公告)号：US10826429B2

公开(公告)日：2020-11-03

申请号：US16172926

申请日：2018-10-29

Applicant: MEDIATEK Inc.

Inventor： Keng-Meng Chang ,  Yun-Chen Chuang ,  Yao-Chi Wang

IPC: H03B5/12 ,  H03B5/04 ,  H03L7/099 ,  H03L1/00 ,  H02M3/158

Abstract: A compensation module, an oscillation circuit and associated compensation method for reducing an oscillation frequency variation in an output oscillation signal of a voltage-controlled oscillator (VCO) core are provided. The compensation module includes a compensation circuit and a polarity selection circuit. The compensation circuit has a capacitance value related to voltages of a first and a second receiving terminals. The oscillation frequency variation is changed with the capacitance value. The polarity selection circuit conducts a periodic regulated signal to one of the first receiving terminal and the second receiving terminal. The polarity selection circuit conducts a filtered bias signal to the other of the first receiving terminal and the second receiving terminal. The periodic regulated signal is sensitive to a regulated voltage variation, and the filtered bias signal is insensitive to the regulated voltage variation.

公开(公告)号：US20170090426A1

公开(公告)日：2017-03-30

申请号：US15244132

申请日：2016-08-23

Applicant: MEDIATEK Inc.

Inventor： Yun-Chen Chuang ,  Ang-Sheng Lin

IPC: G04F10/00 ,  H03L7/093 ,  H03L7/091 ,  H03L7/099

CPC classification number: G04F10/005 ,  H03L7/085 ,  H03L7/16 ,  H03L2207/50

Abstract: A time-to-digital system and associated frequency synthesizer are provided. The time-to-digital system receives a reference clock and a variable clock. The time-to-digital system includes a supplement circuit and a time-to-digital converter (TDC). The supplement circuit generates a delayed reference clock signal and at least one pulse of a variable clock ahead of a transition of the delayed reference clock signal. The delayed reference clock signal is generated according to a delay control signal and the reference clock signal. The delay control signal is determined in response to transitions of the variable clock, and frequency of the variable clock is significantly higher than frequency of the reference clock signal. Being coupled to the supplement circuit, the TDC receives the delayed reference clock signal and the at least one pulse of the variable clock and accordingly produces a TDC signal.