公开(公告)号：US20230396215A1

公开(公告)日：2023-12-07

申请号：US18088612

申请日：2022-12-25

Applicant: MEDIATEK INC.

Inventor： Keng-Meng Chang ,  Sen-You Liu ,  Yao-Chi Wang

IPC: H03B5/32

CPC classification number: H03B5/32 ,  H03B2200/005 ,  H03B2200/0042 ,  H03B2200/0058

Abstract: A reconfigurable crystal oscillator and a method for reconfiguring a crystal oscillator are provided. The reconfigurable crystal oscillator includes a transconductance circuit, a feedback resistor, a crystal tank, an input-end capacitor and an output-end capacitor. Both of the feedback resistor and the crystal tank are coupled between an input terminal and an output terminal of the transconductance circuit. The input-end capacitor is coupled to the input terminal of the transconductance circuit, and the output-end capacitor is coupled to the output terminal of the transconductance circuit. In particular, the transconductance circuit is configured to provide a transconductance, and when an operation mode of the reconfigurable crystal oscillator is switched, an input-end capacitance of the input-end capacitor and an output-end capacitance of the output-end capacitor are switched, respectively.

公开(公告)号：US20220209714A1

公开(公告)日：2022-06-30

申请号：US17693454

申请日：2022-03-14

Applicant: MEDIATEK INC.

Inventor： Sen-You Liu ,  Chien-Wei Chen ,  Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03B5/36

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range. For example, the specific voltage range is determined according to a second voltage level.

公开(公告)号：US11342884B2

公开(公告)日：2022-05-24

申请号：US17306959

申请日：2021-05-04

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Yu-Li Hsueh ,  Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03B5/36 ,  H03K19/21

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may generate a reset signal including at least one reset pulse for resetting the bias voltage. In addition, the reset signal is generated without calibrating the at least one reset pulse to a zero-crossing point of the sinusoidal wave.

公开(公告)号：US09531358B2

公开(公告)日：2016-12-27

申请号：US14685607

申请日：2015-04-14

Applicant: MEDIATEK INC.

Inventor： Sheng-Che Tseng ,  Yao-Chi Wang

IPC: H03K3/017 ,  H03K5/06 ,  H03K19/21 ,  H03K5/156

CPC classification number: H03K5/06 ,  H03K5/1565 ,  H03K19/21

Abstract: A signal generating system for generating an output signal with a 50% duty cycle, comprising: a frequency dividing module, comprising an odd number of level triggering devices, for generating a plurality of frequency divided signals utilizing a frequency dividing ratio equaling to M, wherein the M is an positive integer; and a signal combining module, for combining at least two of the frequency divided signals to generate at least one output combined signal. The signal generating system generates the output signal based on the output combined signal. The frequency dividing module cooperates the signal combining module to provide a frequency dividing ratio equaling to N.5, wherein the N is a positive integer.

Abstract translation: 一种用于产生具有50％占空比的输出信号的信号发生系统，包括：分频模块，包括奇数级触发装置，用于利用等于M的分频比来产生多个分频信号，其中 M是正整数; 以及信号组合模块，用于组合至少两个所述分频信号以产生至少一个输出组合信号。 信号发生系统基于输出组合信号产生输出信号。 分频模块协同信号组合模块提供等于N.5的分频比，其中N是正整数。

公开(公告)号：US11606063B2

公开(公告)日：2023-03-14

申请号：US17695863

申请日：2022-03-16

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Yu-Li Hsueh ,  Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03B5/36 ,  H03K19/21

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator includes a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may provide an alternating current (AC) ground path for noise on the bias voltage according to a reset pulse, wherein a position of the reset pulse is set by a control voltage on a control terminal of the phase noise reduction circuit.

公开(公告)号：US20220209715A1

公开(公告)日：2022-06-30

申请号：US17695863

申请日：2022-03-16

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Yu-Li Hsueh ,  Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03B5/36 ,  H03K19/21

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator includes a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may provide an alternating current (AC) ground path for noise on the bias voltage according to a reset pulse, wherein a position of the reset pulse is set by a control voltage on a control terminal of the phase noise reduction circuit.

公开(公告)号：US11309835B2

公开(公告)日：2022-04-19

申请号：US17306960

申请日：2021-05-04

Applicant: MEDIATEK INC.

Inventor： Sen-You Liu ,  Chien-Wei Chen ,  Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03B5/36

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range.

公开(公告)号：US09906209B2

公开(公告)日：2018-02-27

申请号：US15498525

申请日：2017-04-27

Applicant: MEDIATEK Inc.

Inventor： Keng-Meng Chang ,  Yao-Chi Wang

IPC: H03K19/003 ,  H04B1/00 ,  H03L7/00 ,  H03H11/30 ,  H03K5/159 ,  H03K19/0175 ,  H03K19/00 ,  H04B1/04 ,  H04B1/16 ,  H04L25/02 ,  H03L1/02 ,  H03L7/18 ,  H03L7/10 ,  H03L7/113 ,  H03K19/21

CPC classification number: H03H11/30 ,  H03K5/159 ,  H03K19/0005 ,  H03K19/017545 ,  H03K19/21 ,  H03L1/00 ,  H03L1/022 ,  H03L7/0816 ,  H03L7/103 ,  H03L7/113 ,  H03L7/18 ,  H04B1/0475 ,  H04B1/1638 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292

Abstract: A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance.

公开(公告)号：US20170012584A1

公开(公告)日：2017-01-12

申请号：US15098307

申请日：2016-04-13

Applicant: MEDIATEK INC.

Inventor： Yueh-Ting Lee ,  Yao-Chi Wang ,  Sheng-Che Tseng

IPC: H03B27/00 ,  H03K5/14 ,  H03K21/02 ,  H03L7/00

CPC classification number: H03B27/00 ,  H03K5/14 ,  H03K21/02 ,  H03K2005/00234 ,  H03L7/00 ,  H03L7/0812

Abstract: A circuit for generating a plurality of oscillating signals with different phases includes a frequency divider, a first delay chain, a second delay chain and a calibration circuit. The frequency divider is arranged for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal. The first delay chain is arranged for delaying the first frequency-divided input signal, and the second delay chain is arranged for delaying the second frequency-divided input signal. The calibration circuit is arranged for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain; wherein output signals of a portion delay cells within the first delay chain and the second delay chain serve as the plurality of oscillating signals with different phases.

Abstract translation: 用于产生具有不同相位的多个振荡信号的电路包括分频器，第一延迟链，第二延迟链和校准电路。 分频器被布置用于对第一输入信号和第二输入信号进行分频，以产生第一分频输入信号和第二分频输入信号。 第一延迟链被布置用于延迟第一分频输入信号，并且第二延迟链被布置用于延迟第二分频输入信号。 校准电路被配置为根据第一延迟链或第二延迟链内的信号来控制第一延迟链和第二延迟链的延迟量; 其中所述第一延迟链和所述第二延迟链内的部分延迟单元的输出信号用作具有不同相位的多个振荡信号。

公开(公告)号：US12047038B2

公开(公告)日：2024-07-23

申请号：US18088612

申请日：2022-12-25

Applicant: MEDIATEK INC.

Inventor： Keng-Meng Chang ,  Sen-You Liu ,  Yao-Chi Wang

IPC: H03B5/32 ,  H03B5/36

CPC classification number: H03B5/32 ,  H03B5/366 ,  H03B2200/0042 ,  H03B2200/005 ,  H03B2200/0058 ,  H03B2200/009

Abstract: A reconfigurable crystal oscillator and a method for reconfiguring a crystal oscillator are provided. The reconfigurable crystal oscillator includes a transconductance circuit, a feedback resistor, a crystal tank, an input-end capacitor and an output-end capacitor. Both of the feedback resistor and the crystal tank are coupled between an input terminal and an output terminal of the transconductance circuit. The input-end capacitor is coupled to the input terminal of the transconductance circuit, and the output-end capacitor is coupled to the output terminal of the transconductance circuit. In particular, the transconductance circuit is configured to provide a transconductance, and when an operation mode of the reconfigurable crystal oscillator is switched, an input-end capacitance of the input-end capacitor and an output-end capacitance of the output-end capacitor are switched, respectively.