公开(公告)号：US12289388B2

公开(公告)日：2025-04-29

申请号：US17868841

申请日：2022-07-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich

IPC: H04L7/027 ,  H04L12/40

Abstract: In one embodiment, a clock syntonization system includes a first compute node including a first physical hardware clock to operate at a first clock frequency, a second compute node, and an interconnect data bus to transfer data from the first compute node at a data rate indicative of the first clock frequency of the first physical hardware clock, and wherein the second compute node includes clock synchronization circuitry to derive a second clock frequency from the data rate of the transferred data, and provide a clock signal at the derived second clock frequency.

公开(公告)号：US20250080315A1

公开(公告)日：2025-03-06

申请号：US18950255

申请日：2024-11-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Ariel Shahar ,  Shahaf Shuler ,  Ariel Almog ,  Eitan Hirshberg ,  Natan Manevich

IPC: H04L7/00

Abstract: A communication system includes at least one send queue, containing send queue entries pointing to packets to be transmitted over a network by packet sending circuitry. A clock work queue contains clock queue entries to synchronize sending times of the packets pointed to by the send queue entries. At least one arming queue contains arming queue entries to arm the clock work queue at selected time intervals.

公开(公告)号：US20250055668A1

公开(公告)日：2025-02-13

申请号：US18448936

申请日：2023-08-13

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Arnon Sattinger ,  Wojciech Wasko ,  Maciej Machnikowski ,  Doron Fael ,  Ofir Sadeh ,  Jonathan Oliel

IPC: H04L7/033 ,  H03L7/099 ,  H04L7/10

Abstract: In one embodiment, a system includes a digitally controlled oscillator (DCO) to generate a local clock having a local clock frequency, and clock synchronization circuitry to receive from a device a signal indicative of a remote clock frequency, compare measures of the remote clock frequency and the local clock frequency; generate a digital control command based on the comparison; and provide the digital control command to the DCO, wherein the DCO is to adjust the local clock frequency responsively to the digital control command.

公开(公告)号：US20240373380A1

公开(公告)日：2024-11-07

申请号：US18228505

申请日：2023-07-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Eitan Zahavi ,  Yuval Shpigelman ,  Guy Lederman ,  Liron Mula ,  Omer Shabtai

IPC: H04W56/00

Abstract: A system including a device coupled with a link and including a transmitter. The device is to generate a first control block for synchronization via a physical layer of the link, the first control block including a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits indicating to perform a synchronization handshake. The device is further to transmit, via the link, the first control block comprising the header portion set of bits and the data portion of bit.

公开(公告)号：US12111681B2

公开(公告)日：2024-10-08

申请号：US17313026

申请日：2021-05-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Itai Levy ,  Dotan David Levi ,  Nir Nitzani ,  Natan Manevich ,  Alex Vaynman ,  Ariel Almog

IPC: G06F1/12 ,  G06F13/20 ,  H04L7/00

CPC classification number: G06F1/12 ,  G06F13/20 ,  H04L7/0012

Abstract: A network adapter includes a network port for communicating with a communication network, a hardware clock, and circuitry. The circuitry is coupled to receive from the communication network, via the network port, one or more time-protocol packets that convey a network time used for synchronizing network devices in the communication network, to align the hardware clock to the network time conveyed in the time-protocol packets, and to make the network time available to one or more time-service consumers running in a host served by the network adapter.

公开(公告)号：US12101239B2

公开(公告)日：2024-09-24

申请号：US18106953

申请日：2023-02-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Roee Moyal

IPC: H04L12/00 ,  H04J3/06 ,  H04L43/0888 ,  H04L47/22 ,  H04L47/25 ,  H04L47/263

CPC classification number: H04L43/0888 ,  H04J3/0652 ,  H04J3/0667 ,  H04L47/225 ,  H04L47/25 ,  H04L47/263

Abstract: A system includes a device coupled to a processing device. The processing device is to receive a request to execute a plurality of workloads, the request comprising a rate to execute each workload of the plurality of workloads and a parameter value indicating an execution offset. The processing device is further to determine a sequence for executing the plurality of workloads based on receiving the rate and the parameter value, where the sequence is to execute each workload at the respective rate and each workload of the plurality of workloads is executed at a different time based on the parameter value. The processing device is to execute the plurality of workloads in accordance with the sequence upon determining the sequence to execute the plurality of workloads.

公开(公告)号：US20240244228A1

公开(公告)日：2024-07-18

申请号：US18096430

申请日：2023-01-12

Applicant: Mellanox Technologies, Ltd.

Inventor： Eshed Ram ,  Dotan David Levi ,  Assaf Hallak ,  Shie Mannor ,  Gal Chechik ,  Eyal Frishman ,  Ohad Markus ,  Dror Porat ,  Assaf Weissman

IPC: H04N19/149 ,  H04N19/172

CPC classification number: H04N19/149 ,  H04N19/172

Abstract: A system includes a processing device to receive video content and output encoded video of the video content for a client video device. The system includes a controller coupled to the processing device, the controller programmed with machine instructions to receive, from a video encoder while encoding the video content, frame statistics based on one or more encoded frames of the video content corresponding to a current frame. The machine instructions further generate a first quantization parameter (QP) value for the current frame using a frame machine learning model, wherein the frame machine learning model includes states that depend on the frame statistics. The machine instructions further provide the first QP value to the video encoder for rate control of the frame encoding of the current frame.

公开(公告)号：US20240213996A1

公开(公告)日：2024-06-27

申请号：US18101675

申请日：2023-01-26

Applicant: Mellanox Technologies, Ltd.

Inventor： Wojciech Wasko ,  Mathias Blake ,  Dotan David Levi ,  Adam Thompson ,  Dimitris Syrivelis ,  Paraskevas Bakopoulos

IPC: H03M1/12

CPC classification number: H03M1/124

Abstract: Embodiments described herein can enable minimum processing performed at a signal device level, such that the majority of the non-domain-specific processing can be offloaded to a processing device. For example, the processing device can receive signal data from a signal device, preprocess the signal data to obtain preprocessed signal data having a data format for domain-specific processing by software executed by at least one processing unit of a processing platform, and provide the preprocessed signal data for domain-specific processing by the software executed by the at least one processing unit.

公开(公告)号：US20240204897A1

公开(公告)日：2024-06-20

申请号：US18067767

申请日：2022-12-19

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Natan Manevich ,  Dotan David Levi ,  Maciek Machnikowski ,  Wojciech Wasko ,  Bar Shapira ,  Jonathan Oliel ,  Ofir Sadeh

IPC: H04J3/06

CPC classification number: H04J3/0667

Abstract: In one embodiment, a processing system includes an interface controller to receive a data signal from a remote link partner over a link, and recover a clock signal from the received data signal, frequency generation circuitry to receive the recovered clock signal, and output a local clock signal responsively to the received recovered clock signal, wherein the interface controller is configured to drive a transmit symbol rate responsively to the local clock signal, and a digital control loop including the interface controller and the frequency generation circuitry, wherein the interface controller is configured to identify a clock drift, generate a digital control signal responsively to the clock drift, and send the digital control signal to the frequency generation circuitry, which is configured to adjust a frequency of the local clock signal responsively to the digital control signal in order to reduce the clock drift.

公开(公告)号：US20240064443A1

公开(公告)日：2024-02-22

申请号：US17948930

申请日：2022-09-20

Applicant: Mellanox Technologies, Ltd.

Inventor： Ioannis (Giannis) Patronas ,  Paraskevas Bakopoulos ,  Dotan David Levi ,  Aviv Berg ,  Wojciech Wasko ,  Dimitrios Syrivelis ,  Elad Mentovich ,  Yoav Rozenberg ,  Nikolaos Argyris

IPC: H04Q11/00

CPC classification number: H04Q11/0005 ,  H04Q11/0062 ,  H04Q2011/0007 ,  H04Q2011/0037 ,  H04Q2011/0064

Abstract: Systems, devices, and methods are described herein for reducing a link bringup time period for optical switching between network devices. An example method of the present disclosure receives an indication of a reconfiguration condition associated with an optical switch communicatively coupled to an optical communication channel and based on the reconfiguration condition, selects first data associated with a storage device or second data associated with a pattern generator device for transmission to a first network device. Selecting the first or second data may be based on a digital logic signal that indicates whether data is actively received from the second network device via the optical communication channel or may be based on a defined schedule for reconfiguring the optical switch.