公开(公告)号：US11594272B2

公开(公告)日：2023-02-28

申请号：US17409608

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Adam S. El-Mansouri ,  Suryanarayana B. Tatapudi ,  John D. Porter

IPC: G11C11/22

Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

公开(公告)号：US10998026B2

公开(公告)日：2021-05-04

申请号：US16813319

申请日：2020-03-09

Applicant: Micron Technology, Inc.

Inventor： Adam S. El-Mansouri ,  David L. Pinney

IPC: G11C11/22 ,  G11C8/10 ,  G11C8/08

Abstract: Methods, systems, and devices for ferroelectric memory plate power reduction are described. A plate line may be coupled with a voltage source, a capacitor, and one or more sections of a bank of ferroelectric memory cells. During a write operation, the capacitor may be discharged onto the plate line and the resulting voltage may be adjusted (e.g., increased) by the voltage source before writing one or more memory cells. During a write-back operation, a capacitor associated with one or more memory cells may be discharged onto the plate line and stored at the capacitor. The charge may be re-applied to the plate line and adjusted (e.g., increased) by the voltage source during the write-back.

公开(公告)号：US20190333562A1

公开(公告)日：2019-10-31

申请号：US15962938

申请日：2018-04-25

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Adam S. El-Mansouri ,  Suryanarayana B. Tatapudi ,  John D. Porter

IPC: G11C11/22

Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

公开(公告)号：US20200219551A1

公开(公告)日：2020-07-09

申请号：US16825832

申请日：2020-03-20

Applicant: Micron Technology, Inc.

Inventor： Adam S. El-Mansouri ,  David L. Pinney

IPC: G11C11/22 ,  G11C8/10 ,  G11C8/08

Abstract: Methods, systems, and devices for cell voltage accumulation discharge are described. One or more sections of a bank of ferroelectric memory cells may be coupled with one or more access lines. By activating one or more switching components, one or more sections (that may include a memory array and/or a driver) of memory cells may be isolated. When isolated, a voltage may be applied across an access line associated with the section to activate an access device of each memory cell. By activating a switching component of a respective memory cell, a capacitor of the memory cell may be discharged and then the isolated section may be coupled with the plurality of access lines.

公开(公告)号：US20200211613A1

公开(公告)日：2020-07-02

申请号：US16813319

申请日：2020-03-09

Applicant: Micron Technology, Inc.

Inventor： Adam S. El-Mansouri ,  David L. Pinney

IPC: G11C11/22 ,  G11C8/10 ,  G11C8/08

Abstract: Methods, systems, and devices for ferroelectric memory plate power reduction are described. A plate line may be coupled with a voltage source, a capacitor, and one or more sections of a bank of ferroelectric memory cells. During a write operation, the capacitor may be discharged onto the plate line and the resulting voltage may be adjusted (e.g., increased) by the voltage source before writing one or more memory cells. During a write-back operation, a capacitor associated with one or more memory cells may be discharged onto the plate line and stored at the capacitor. The charge may be re-applied to the plate line and adjusted (e.g., increased) by the voltage source during the write-back.

公开(公告)号：US20190081024A1

公开(公告)日：2019-03-14

申请号：US16190523

申请日：2018-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Adam S. El-Mansouri ,  Fuad Badrieh ,  Brent Keeth

IPC: H01L25/065 ,  G05F1/10

CPC classification number: H01L25/0657 ,  G05F1/10 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541

Abstract: Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit board that regulates a first voltage; a semiconductor device on the circuit board that receives the first voltage through a power line in the circuit board. The semiconductor device includes: a substrate on the circuit board, stacked via conductive balls, that receives the first voltage from the power line via the conductive balls; a plurality of dies on the semiconductor device, stacked via bumps, each die including, a first conductive via that receives the first voltage via the bumps; a plurality of pillars between adjacent dies and couple the first conductive vias of the adjacent dies; and a sense node switch circuit that selectively couples one first conductive via of one die among the plurality of dies to the regulator.

公开(公告)号：US20180308538A1

公开(公告)日：2018-10-25

申请号：US15957742

申请日：2018-04-19

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Adam S. El-Mansouri

IPC: G11C11/22 ,  G11C7/06 ,  H01L27/11502

Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.

公开(公告)号：US11699475B2

公开(公告)日：2023-07-11

申请号：US17236724

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Adam S. El-Mansouri ,  David L. Pinney

IPC: G11C11/22 ,  G11C8/10 ,  G11C8/08

CPC classification number: G11C11/221 ,  G11C8/08 ,  G11C8/10 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293

Abstract: Methods, systems, and devices for ferroelectric memory plate power reduction are described. A plate line may be coupled with a voltage source, a capacitor, and one or more sections of a bank of ferroelectric memory cells. During a write operation, the capacitor may be discharged onto the plate line and the resulting voltage may be adjusted (e.g., increased) by the voltage source before writing one or more memory cells. During a write-back operation, a capacitor associated with one or more memory cells may be discharged onto the plate line and stored at the capacitor. The charge may be re-applied to the plate line and adjusted (e.g., increased) by the voltage source during the write-back.

公开(公告)号：US11127449B2

公开(公告)日：2021-09-21

申请号：US15962938

申请日：2018-04-25

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Adam S. El-Mansouri ,  Suryanarayana B. Tatapudi ,  John D. Porter

IPC: G11C11/22

Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

公开(公告)号：US10667621B2

公开(公告)日：2020-06-02

申请号：US15957742

申请日：2018-04-19

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Adam S. El-Mansouri

IPC: G11C11/22 ,  A47C20/00 ,  G11C7/06 ,  A47C13/00 ,  A47C17/02 ,  H01L27/11502

Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.