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    Grindable heat sink for multiple die packaging
    1.
    发明授权
    Grindable heat sink for multiple die packaging 有权

    公开(公告)号：US12300570B2

    公开(公告)日：2025-05-13

    申请号：US17583038

    申请日：2022-01-24

    Applicant: Micron Technology, Inc.

    Inventor： Wei Zhou ,  Bret K. Street ,  Kyle K. Kirby

    IPC: H01L23/373 ,  H01L21/56 ,  H01L21/603 ,  H01L23/31 ,  H01L23/544 ,  H01L25/16

    Abstract: A semiconductor package can include a semiconductor die stack including a top die and one or more core dies below the top die. The semiconductor package can further include a metal heat sink plated on a top surface of the top die and have a plurality of side surfaces coplanar with corresponding ones of a plurality of sidewalls of the semiconductor die stack. A molding can surround the stack of semiconductor dies and the metal heat sink, the molding including a top surface coplanar with an exposed upper surface of the metal heat sink. The top surface of the molding and the exposed upper surface of the metal heat sink are both mechanically altered. For example, the metal heat sink and the molding can be simultaneously ground with a grinding disc and can show grinding marks as a result.

    CONDUCTIVE PAD ON A THROUGH-SILICON VIA
    2.
    发明申请
    CONDUCTIVE PAD ON A THROUGH-SILICON VIA 有权

    公开(公告)号：US20240379596A1

    公开(公告)日：2024-11-14

    申请号：US18660210

    申请日：2024-05-09

    Applicant: Micron Technology, Inc.

    Inventor： Bharat Bhushan ,  Terrence B. McDaniel ,  Kunal R. Parekh ,  Bret K. Street ,  Akshay N. Singh

    IPC: H01L23/00 ,  H01L21/311 ,  H01L23/48 ,  H01L25/065

    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a front side and a back side opposite the front side. A through via extends entirely through the substrate. The through via includes a protruding portion that extends beyond the back side of the substrate. A layer of silicon carbon nitride is disposed at the back side of the substrate and along sidewalls of the protruding portion of the through via. A layer of oxide is disposed at the back side of the substrate and at least partially surrounding the protruding portion of the through via. A conductive pad is disposed at a coupling surface of the through via and at least partially extending through the layer of oxide. As a result, a reliable and cost-efficient semiconductor device can be assembled.

    Die features for self-alignment during die bonding
    6.
    发明授权
    Die features for self-alignment during die bonding 有权

    公开(公告)号：US11302653B2

    公开(公告)日：2022-04-12

    申请号：US16993860

    申请日：2020-08-14

    Applicant: Micron Technology, Inc.

    Inventor： Bret K. Street ,  Wei Zhou ,  Christopher J. Gambee ,  Jonathan S. Hacker ,  Shijian Luo

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

    Abstract: A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

    Combination-bonded die pair packaging and associated systems and methods
    7.
    发明授权
    Combination-bonded die pair packaging and associated systems and methods 有权

    公开(公告)号：US11289440B1

    公开(公告)日：2022-03-29

    申请号：US17035579

    申请日：2020-09-28

    Applicant: Micron Technology, Inc.

    Inventor： Kyle K. Kirby ,  Bret K. Street

    IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00

    Abstract: Systems and methods for semiconductor devices having a substrate with bond pads, a die pair in a stacked configuration above the bond pads and having a first die having an oxide layer, a second die having an oxide layer attached to the first oxide layer, and conductive bonds electrically coupling the dies. Interconnects extend between the bond pads and the die pair, electrically coupling die pair to the substrate. The device may include a second die pair electrically coupled to: (1) the first die pair with secondary interconnects; and (2) the substrate with through-silicon vias extending through the first die pair. The top die of a die pair may be a thick die for use at the top of a pair stack. Pairs may be created by matching dies of a first silicon wafer to dies of a second silicon wafer, combination bonding the wafers, and dicing the die pairs.

    Semiconductor device with a layered protection mechanism and associated systems, devices, and methods
    8.
    发明授权
    Semiconductor device with a layered protection mechanism and associated systems, devices, and methods 有权

    公开(公告)号：US11114415B2

    公开(公告)日：2021-09-07

    申请号：US16823028

    申请日：2020-03-18

    Applicant: Micron Technology, Inc.

    Inventor： Wei Zhou ,  Bret K. Street

    IPC: H01L23/48 ,  H01L25/065 ,  H01L23/495 ,  H01L25/00 ,  H01L23/64 ,  H01L21/56 ,  H01L23/36

    Abstract: A semiconductor device includes a first die; a second die attached over the first die; a metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level; wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.

    Electrically or Temperature Activated Shape-Memory Materials for Warpage Control
    9.
    发明申请
    Electrically or Temperature Activated Shape-Memory Materials for Warpage Control 有权

    公开(公告)号：US20210066212A1

    公开(公告)日：2021-03-04

    申请号：US16950379

    申请日：2020-11-17

    Applicant: Micron Technology, Inc.

    Inventor： Bret K. Street

    IPC: H01L23/00 ,  H01L23/373 ,  H01L21/326 ,  H01L21/324

    Abstract: A semiconductor device assembly including a shape-memory element connected to at least one component of the semiconductor device assembly. The shape-memory element may be temperature activated or electrically activated. The shape-memory element is configured to move to reduce, minimize, or modify a warpage of a component of the assembly by moving to an initial shape. The shape-memory element may be applied to a surface of a component of the semiconductor device assembly or may be positioned within a component of the semiconductor device assembly such as a layer. The shape-memory element may be connected between two components of the semiconductor device assembly. A plurality of shape-memory elements may be used to reduce, minimize, and/or modify warpage of one or more components of a semiconductor device assembly.

    Die features for self-alignment during die bonding
    10.
    发明授权
    Die features for self-alignment during die bonding 有权

    公开(公告)号：US10748857B2

    公开(公告)日：2020-08-18

    申请号：US16127769

    申请日：2018-09-11

    Applicant: Micron Technology, Inc.

    Inventor： Bret K. Street ,  Wei Zhou ,  Christopher J. Gambee ,  Jonathan S. Hacker ,  Shijian Luo

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

    Abstract: A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

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