公开(公告)号：US20170285938A1

公开(公告)日：2017-10-05

申请号：US15084979

申请日：2016-03-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G06F3/06 ,  G11C16/26 ,  G06F12/08 ,  G11C16/32

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0802 ,  G06F2212/222 ,  G06F2212/7203 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/26 ,  G11C16/32

Abstract: In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.

公开(公告)号：US09478270B2

公开(公告)日：2016-10-25

申请号：US14918249

申请日：2015-10-20

Applicant: Micron Technology, Inc.

Inventor： Eric Lee

IPC: G11C7/00 ,  G11C8/00 ,  G11C8/18 ,  G11C7/22 ,  G06F1/08 ,  G11C7/10

CPC classification number: G11C7/222 ,  G06F1/08 ,  G11C7/10 ,  G11C7/1063 ,  G11C7/1069 ,  G11C7/22 ,  G11C8/18

Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.

公开(公告)号：US20230066951A1

公开(公告)日：2023-03-02

申请号：US17465033

申请日：2021-09-02

Applicant: Micron Technology, Inc.

Inventor： Sundararajan N. Sankaranarayanan ,  Eric Lee

IPC: G06F12/0815

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device perform operations comprising receiving a sequence of read commands from a memory sub-system controller; retrieving first data by executing a first read command of the set of read commands; storing the first data in a first portion of a cache of the memory device; responsive to determining that the memory device is in a suspended state, determining whether a first address range specified by the first read command overlaps with a second address range specified by a second read command of the set of read commands; responsive to determining that the first address range does not overlap with the second address range, retrieving second data by executing the second read command and storing the second data in a second portion of the cache; transferring the first and second data to the controller.

公开(公告)号：US10802721B2

公开(公告)日：2020-10-13

申请号：US16398646

申请日：2019-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G11C7/10 ,  G06F3/06 ,  G11C16/32 ,  G11C16/26 ,  G06F12/0802 ,  G11C7/22 ,  G06F12/02

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal; to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal; and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

公开(公告)号：US20190258400A1

公开(公告)日：2019-08-22

申请号：US16398646

申请日：2019-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/32 ,  G11C7/10 ,  G11C7/22 ,  G06F12/0802 ,  G06F12/02

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal; to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal; and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

公开(公告)号：US11604732B1

公开(公告)日：2023-03-14

申请号：US17465033

申请日：2021-09-02

Applicant: Micron Technology, Inc.

Inventor： Sundararajan N. Sankaranarayanan ,  Eric Lee

IPC: G06F12/0815 ,  G06F3/06 ,  G06F12/02

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device perform operations comprising receiving a sequence of read commands from a memory sub-system controller; retrieving first data by executing a first read command of the set of read commands; storing the first data in a first portion of a cache of the memory device; responsive to determining that the memory device is in a suspended state, determining whether a first address range specified by the first read command overlaps with a second address range specified by a second read command of the set of read commands; responsive to determining that the first address range does not overlap with the second address range, retrieving second data by executing the second read command and storing the second data in a second portion of the cache; transferring the first and second data to the controller.

公开(公告)号：US20180292990A1

公开(公告)日：2018-10-11

申请号：US16006192

申请日：2018-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G06F3/06 ,  G11C16/32 ,  G11C16/26 ,  G11C7/22 ,  G11C7/10 ,  G06F12/0802

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0215 ,  G06F12/0802 ,  G06F2212/1016 ,  G06F2212/2022 ,  G06F2212/222 ,  G06F2212/7203 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/26 ,  G11C16/32

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

公开(公告)号：US10019170B2

公开(公告)日：2018-07-10

申请号：US15084979

申请日：2016-03-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/32 ,  G06F12/0802 ,  G11C7/10 ,  G11C7/22

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0215 ,  G06F12/0802 ,  G06F2212/1016 ,  G06F2212/2022 ,  G06F2212/222 ,  G06F2212/7203 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/26 ,  G11C16/32

Abstract: In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.

公开(公告)号：US20140233324A1

公开(公告)日：2014-08-21

申请号：US14259403

申请日：2014-04-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/222 ,  G06F1/08 ,  G11C7/10 ,  G11C7/1063 ,  G11C7/1069 ,  G11C7/22 ,  G11C8/18

Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.

Abstract translation: 公开了用于从存储器提供数据的数据路径，存储器和方法。 读取数据路径的示例包括延迟路径和时钟数据寄存器。 数据路径具有数据传播延迟，并被配置为接收数据并传播数据。 延迟路径被配置为接收时钟信号并提供具有相对于对数据传播延迟建模的时钟信号的延迟的延迟时钟信号。 时钟数据寄存器被配置为至少部分地响应延迟的时钟信号来对数据进行时钟响应。 时钟数据寄存器还被配置为至少部分地基于时钟信号来时钟输出数据。

公开(公告)号：US20230176972A1

公开(公告)日：2023-06-08

申请号：US18104897

申请日：2023-02-02

Applicant: Micron Technology, Inc.

Inventor： Sundararajan N. Sankaranarayanan ,  Eric Lee

IPC: G06F12/0815 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F12/0815 ,  G06F3/0659 ,  G06F12/0246 ,  G06F3/0611 ,  G06F3/0679 ,  G06F2212/1024

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device perform operations comprising receiving, from a memory sub-system controller, a first read command and a second read command; determining that the memory device is in a suspended state; and responsive to determining that a first address range specified by the first read command does not overlap with a second address range specified by the second read command, issuing, to the memory device, the first read command and the second read command collectively.