公开(公告)号：US08976600B2

公开(公告)日：2015-03-10

申请号：US14046428

申请日：2013-10-04

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Ti Wen Chen ,  Shuo-Nan Hung ,  Shih-Lin Huang

IPC: G11C16/06 ,  G11C16/16

CPC classification number: G11C16/16 ,  G11C16/08 ,  G11C16/12

Abstract: A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage. In a second mode, the first transistor decouples the word line from the global word line, and the second transistor couples the word line to the ground voltage.

Abstract translation: 存储电路包括耦合到存储器阵列的字线，包括在擦除操作中取消选择的一个或多个字线的第一组以及在擦除操作中选择的一个或多个字线的第二组。 响应于接收到擦除操作的擦除命令，控制电路将擦除操作中未选择的一个或多个字线的第一组耦合到参考电压。 一些示例还包括可将字线可切换地耦合到全局字线的第一晶体管，以及可切换地将字线耦合到接地电压的第二晶体管。 控制电路耦合到第一晶体管和第二晶体管，其中控制电路具有包括至少擦除操作的多个模式。 在第一模式中，第一晶体管将字线耦合到全局字线，并且第二晶体管将字线与接地电压分离。 在第二模式中，第一晶体管将字线与全局字线分离，并且第二晶体管将字线耦合到接地电压。

公开(公告)号：US20140254284A1

公开(公告)日：2014-09-11

申请号：US14046428

申请日：2013-10-04

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Ti Wen Chen ,  Shuo-Nan Hung ,  Shih-Lin Huang

IPC: G11C16/16

CPC classification number: G11C16/16 ,  G11C16/08 ,  G11C16/12

Abstract: A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage. In a second mode, the first transistor decouples the word line from the global word line, and the second transistor couples the word line to the ground voltage.

Abstract translation: 存储器电路包括耦合到存储器阵列的字线，包括在擦除操作中取消选择的一个或多个字线的第一组以及在擦除操作中选择的一个或多个字线的第二组。 响应于接收到擦除操作的擦除命令，控制电路将擦除操作中未选择的一个或多个字线的第一组耦合到参考电压。 一些示例还包括可将字线可切换地耦合到全局字线的第一晶体管，以及可切换地将字线耦合到接地电压的第二晶体管。 控制电路耦合到第一晶体管和第二晶体管，其中控制电路具有包括至少擦除操作的多个模式。 在第一模式中，第一晶体管将字线耦合到全局字线，并且第二晶体管将字线与接地电压分离。 在第二模式中，第一晶体管将字线与全局字线分离，并且第二晶体管将字线耦合到接地电压。

公开(公告)号：US08760928B2

公开(公告)日：2014-06-24

申请号：US13710992

申请日：2012-12-11

Applicant: Macronix International Co., Ltd

Inventor： Ti-Wen Chen ,  Hang-Ting Lue ,  Shuo-Nan Hung ,  Shih-Lin Huang ,  Chih-Chang Hsieh ,  Kuo-Pin Chang

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/04 ,  G11C11/56 ,  G11C5/14

CPC classification number: G11C16/26 ,  G11C5/146 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/1157

Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.

Abstract translation: 电荷存储存储器配置在NAND阵列中，并且包括经由串选择开关耦合到位线的NAND串并且包括字线。 控制器被配置为产生用于对NAND阵列的所选单元执行操作的偏置。 该偏置包括在字符串选择开关闭合时对位线进行充电，例如不会将这种位线充电引起的噪声引入串中。 在耦合到所选字线的NAND串中的存储器单元的两侧的存储单元中的半导体主体区域被耦合到参考电压，使得它们被预充电，而阵列中的字符串的字线 在操作期间转变为各种电压。