公开(公告)号：US5512933A

公开(公告)日：1996-04-30

申请号：US135054

申请日：1993-10-12

申请人： Mark A. Wheatley ,  Peter Wilcox

发明人： Mark A. Wheatley ,  Peter Wilcox

IPC分类号： H04H1/00 ,  H04H60/40 ,  H04H60/59 ,  H04N7/00 ,  H04N17/00

CPC分类号： H04H60/59 ,  H04H60/372

摘要： A system for identifying a program stream being displayed at a receiver location comprises means at a central station for measuring the relative luminance of a plurality of predetermined areas in each frame and recording that data with their times of occurrence for each of a plurality of program streams as reference data, and means at a receiver location to measure the relative luminance of the same areas but at a repetition rate less than that at the central station for a given time after a channel change and thereafter at an even lower repetition rate and storing the measurements at the receiver location with times defining corresponding broadcast times, and means for transmitting the stored data to the central station for correlating the measured and reference data using the recorded times to access the corresponding measured values of the recorded and reference data.

摘要翻译： 用于识别在接收器位置处显示的节目流的系统包括在中心站处的装置，用于测量每个帧中的多个预定区域的相对亮度，并且以多个节目流中的每一个的多个节目流中的每一个的时间来记录该数据 作为参考数据，以及在接收器位置处的装置，以测量相同区域的相对亮度，但是在频道改变之后的给定时间内以比在中心站处的重复频率小的重复率，然后以更低的重复率存储 在接收器位置处的测量值与定义相应的广播时间的时间相关联，以及用于将所存储的数据发送到中心站的装置，用于使用记录的时间对测量的和参考数据进行相关，以访问记录的和参考数据的对应的测量值。

公开(公告)号：US4379272A

公开(公告)日：1983-04-05

申请号：US211272

申请日：1980-11-28

申请人： Mark A. Wheatley

发明人： Mark A. Wheatley

IPC分类号： H03G3/20 ,  H03C1/06

CPC分类号： H03G3/3042

摘要： An automatic gain control (AGC) circuit arrangement is disclosed as including an AGC loop responsive to an input signal and operative to maintain an output signal at a desired mean level represented by a reference signal applied in the loop and also subjected to amplitude modulation by an AF signal. The circuit arrangement includes modulators outside the loop for changing the level of the input signal by amounts corresponding respectively to changes in level represented by changes in the AF signal and by changes in the reference signal. Therefore, the level of the input signal as received by the AGC loop is at least approximately at the right value and its gain is held substantially constant even when the level of the required output signal for a given input signal changes. Therefore, variations of bandwidth resulting from gain variations are avoided.

摘要翻译： 公开了一种自动增益控制（AGC）电路装置，其包括响应于输入信号的AGC环路，并且可操作以将输出信号保持在由在环路中施加的参考信号所表示的期望的平均电平，并且还经过幅度调制 自动对焦信号。 该电路装置包括用于改变输入信号电平的调制器，分别对应于由AF信号的变化表示的电平变化以及参考信号的变化。 因此，AGC环路所接收的输入信号的电平至少接近于正确的值，即使给定输入信号的所需输出信号的电平改变，其增益保持基本恒定。 因此，避免了由增益变化引起的带宽变化。

公开(公告)号：US5038120A

公开(公告)日：1991-08-06

申请号：US486781

申请日：1990-03-01

申请人： Mark A. Wheatley ,  Leslie A. Lepper ,  Nigel K. Webb

发明人： Mark A. Wheatley ,  Leslie A. Lepper ,  Nigel K. Webb

IPC分类号： H03C3/02 ,  H03C3/09 ,  H03L7/197

CPC分类号： H03C3/0991 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0975 ,  H03L7/1976 ,  H03C3/02

摘要： A fractional-N type frequency synthesizer has a voltage controlled oscillator controlled in a phase-locked loop by a divide by N divider and a phase comparator responsive to the divided frequency and to a reference frequency Fr. An accumulator is responsive to the desired fractional part of the N and is clocked by Fr to produce carry signals for producing the required periodic variations in N. A second accumulator produces periodic equal and opposite further variations in N to reduce the magnitude of the error waveform which would be given to the phase-detector output by the variations in n caused by the first accumulator. A digital to analog converter and a differentiating circuit produce a jitter correction signal for reducing residual jitter. A coherent detector detects for the presence of any residual jitter at the control input of the VCO and resulting from the fractional-N control circuit. Any such residual jitter produces a control signal which adjusts the value of the jitter correction signal accordingly. Two-port frequency modulation is produced by an in-band circuit incorporating an integrator and a full band circuit. With no FM input, a counter detects any divergence in output frequency from the desired value and caused by spurious input at the integrator. A resultant control signal offsets any such spurious inputs. The coherent detector detects at the control input of the VCO any component which is coherent with the in band modulation signal and adjusts the full band modulation signal to eliminate this, so that correct FM is produced.

摘要翻译： 分数N型频率合成器具有通过除以N除法器和相位比较器在锁相环中控制的压控振荡器，该相位比较器响应于分频和参考频率Fr。 累加器响应于期望的N分数部分并由Fr计时，以产生用于产生N中所需的周期性变化的进位信号。第二个累加器在N中产生周期性相等和相反的其他变化，以减小误差波形的幅度 这将由由第一累加器引起的n的变化给予相位检测器输出。 数模转换器和微分电路产生抖动校正信号，以减少残余抖动。 相干检测器检测在VCO的控制输入处是否存在任何残留抖动，并由分数N控制电路产生。 任何这样的残余抖动产生相应地调整抖动校正信号的值的控制信号。 双端口频率调制由并入有积分器和全频带电路的带内电路产生。 在没有FM输入的情况下，计数器会从所需值检测输出频率的任何偏差，并由积分器的寄生输入引起。 所得到的控制信号抵消任何这样的虚假输入。 相干检测器在VCO的控制输入处检测与带内调制信号相干的任何分量，并调整全频带调制信号以消除该频带调制信号，从而产生正确的FM。