公开(公告)号：US20060179183A1

公开(公告)日：2006-08-10

申请号：US11054372

申请日：2005-02-09

申请人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

发明人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F13/161 ,  G11C5/04

摘要： Multiple write buffers are provided within each memory module and are utilized to buffer multiple received write data forwarded to the chip via a write-to-buffer data operation. When a write is received at the memory controller, the memory controller first issues the write-to-buffer (data) operation and the data is forwarded to one of the write buffers. Multiple writes targeting the same DIMM are thus buffered. When all of the available buffers at a memory module are full, the memory controller issues the set of address only write commands to the memory module. The control logic of the DIMM streams all of the buffered write data to the memory device(s) in one continuous burst. By buffering multiple writes and then writing all buffered write data within the DIMM in a single burst, the write-to-read turnaround penalty of the memory module's data bus is substantially minimized.

摘要翻译： 在每个存储器模块内提供多个写入缓冲器，并且用于经由写入缓冲器数据操作来缓冲转发到芯片的多个接收到的写入数据。 当在存储器控制器处接收到写入时，存储器控制器首先发出写入缓冲器（数据）操作，并将数据转发到写入缓冲器之一。 因此，针对同一DIMM的多个写入被缓存。 当内存模块中的所有可用缓冲区都已满时，内存控制器会向内存模块发出一组仅地址写入命令。 DIMM的控制逻辑将所有缓冲的写入数据以一个连续的脉冲串流式传输到存储器件。 通过缓冲多个写入，然后以单个脉冲串将所有缓冲的写入数据写入DIMM内，内存模块的数据总线的写入读取周转损失基本上最小化。

公开(公告)号：US20060179206A1

公开(公告)日：2006-08-10

申请号：US11054066

申请日：2005-02-09

申请人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

发明人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC分类号： G06F12/06

CPC分类号： G06F13/1647 ,  G11C5/04 ,  Y02D10/14

摘要： A set of N copies of bank control logic are provided for tracking the banks within the memory modules (DRAMS). When the total number of banks within the memory module(s) is greater than N, the addresses of particular banks are folded into a single grouping. The banks are represented by the N copies of the bank control logic even when the total number of banks is greater than N. Each bank within the group is tagged as being busy when any one of the banks in the group is the target of a memory access request. The algorithm folds the addresses of the banks in an order that substantially minimizes the likelihood that a bank that is in a busy or false busy state will be the target of another memory access request. Power and logic savings are recognized as only N copies of bank control logic have to be supported.

公开(公告)号：US20080091905A1

公开(公告)日：2008-04-17

申请号：US11951735

申请日：2007-12-06

申请人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

发明人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F13/1626

摘要： Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.

摘要翻译： 内存模块设计有多个写入缓冲器，用于临时保存写入数据。 “写入缓冲”操作将内存控制器中的写入数据移动到写入缓冲区，同时内存模块正忙于处理读取操作。 然后，随后发出仅地址的“写入”命令来将缓冲的写入数据写入存储器件。 针对闲置DIMM的写命令在针对繁忙DIMM（或即将忙于）的写入之前按顺序发出。 通过后台写入缓冲操作移动数据可以提高通用写入数据通道的效率，并允许写入数据总线在重读操作期间达到最大带宽。 实际写入操作，延迟到写入负面影响的时期可以完全/大部分隐藏。 在光读取活动期间，或者当没有读取待处理时，缓冲存储器模块中的数据使缓冲数据能够同时跨多个存储器模块并行编写。

公开(公告)号：US20060179213A1

公开(公告)日：2006-08-10

申请号：US11054447

申请日：2005-02-09

申请人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

发明人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F13/1626

摘要： Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.

摘要翻译： 内存模块设计有多个写入缓冲器，用于临时保存写入数据。 “写入缓冲”操作将内存控制器中的写入数据移动到写入缓冲区，同时内存模块正忙于处理读取操作。 然后，随后发出仅地址的“写入”命令来将缓冲的写入数据写入存储器件。 针对闲置DIMM的写命令在针对繁忙DIMM（或即将忙于）的写入之前按顺序发出。 通过后台写入缓冲操作移动数据可以提高通用写入数据通道的效率，并允许写入数据总线在重读操作期间达到最大带宽。 实际写入操作，延迟到写入负面影响的时期可以完全/大部分隐藏。 在光读取活动期间，或者当没有读取待处理时，缓冲存储器模块中的数据使缓冲数据能够同时跨多个存储器模块并行编写。

公开(公告)号：US20070107921A1

公开(公告)日：2007-05-17

申请号：US11560491

申请日：2006-11-16

申请人： Gary Morrison ,  Lee Perry ,  Rick Sperry

发明人： Gary Morrison ,  Lee Perry ,  Rick Sperry

IPC分类号： H01B11/06

CPC分类号： H01B9/02 ,  H01R4/646 ,  H01R4/66 ,  H01R9/0521

摘要： The product of the present invention comprises flexible tray cables and metal-clad cables designed for use with adjustable speed drives, and terminations coupled therewith. The cables comprise, generally, three phase conductors, three ground conductors and fillers, and are wrapped with copper tape and other elements. The terminations comprise a plurality of connectors and a plurality of flexible, tinned-copper braids acting as the shield termination for the copper tape. More detailed and other embodiments of the present invention are disclosed in the specification hereof.

摘要翻译： 本发明的产品包括柔性托盘电缆和设计用于可调速驱动器的金属覆层电缆，以及与其耦合的端接件。 电缆通常包括三相导体，三个接地导体和填充物，并且用铜带和其它元件包裹。 端子包括多个连接器和多个用作铜带的屏蔽端子的柔性镀锡铜编织带。 在本说明书中公开了本发明的更详细和其它实施例。

公开(公告)号：US5451947A

公开(公告)日：1995-09-19

申请号：US200613

申请日：1994-02-23

申请人： Gary Morrison

发明人： Gary Morrison

IPC分类号： H03M1/48 ,  G01R19/25 ,  G01R21/133 ,  H03M1/20

CPC分类号： G01R19/25 ,  G01R21/133 ,  H03M1/201

摘要： A system for analogue to digital conversion comprising a means (4) for receiving an input analogue signal, a dither generator for adding a dither signal and an analogue to digital converter (2) for converting the combined input signal and dither signal to a digital value, characterized in that the dither generator provides a dither signal of a form comprising a first periodic dither signal having superimposed and being shaped by a second signal having at least one component which varies the first periodic dither signal over at least one quantization interval of the analogue to digital converter.

摘要翻译： 一种用于模数转换的系统，包括用于接收输入模拟信号的装置（4），用于添加抖动信号的抖动发生器和用于将组合输入信号和抖动信号转换成数字值的模数转换器（2） 其特征在于，所述抖动发生器提供包括第一周期性抖动信号的抖动信号，所述第一周期性抖动信号已被叠加并被第二信号整形，所述第二信号具有至少一个分量，所述至少一个分量通过所述模拟信号的至少一个量化间隔改变第一周期性抖动信号 到数字转换器。

公开(公告)号：US20220161300A1

公开(公告)日：2022-05-26

申请号：US17505830

申请日：2021-10-20

申请人： Travis Duffus ,  Gary Morrison

发明人： Travis Duffus ,  Gary Morrison

IPC分类号： B08B9/043

摘要： The present invention relates generally to the field of pump cleaning and unclogging. More specifically, the present invention relates to a tool which allows a user to unclog and remove rags, cloth materials, debris, or other obstructions from submersible and master-station pumps. Further, the invention can be used either as a hand tool or as an attachment to a crane or other machine for power assisted pulling, unclogging, and removal of rags, cloth materials, debris, and other obstructions.

公开(公告)号：US20070260950A1

公开(公告)日：2007-11-08

申请号：US11355681

申请日：2006-02-16

申请人： Gary Morrison ,  Jose Lyon ,  William Moyer ,  Anthony Reipold

发明人： Gary Morrison ,  Jose Lyon ,  William Moyer ,  Anthony Reipold

IPC分类号： G01R31/28

CPC分类号： G01R31/318544 ,  G01R31/318536 ,  G01R31/318552 ,  G06F11/2236

摘要： A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of the user application and, if necessary, saving a state of the at least one logic block of the processor. The method further includes applying a test stimulus for testing the at least one logic block of the processor. The test stimulus may be shifted into scan chains so as to perform scan testing of the processor during normal operation, such as during execution of a user application.

摘要翻译： 用于测试处理器的至少一个逻辑块的方法包括在处理器执行用户应用期间，处理器产生停止和测试指示符。 响应于产生停止和测试指示符，停止执行用户应用程序，并且如果需要，保存处理器的至少一个逻辑块的状态。 该方法还包括应用用于测试处理器的至少一个逻辑块的测试激励。 测试刺激可以被转移到扫描链中，以便在正常操作期间，例如在用户应用的执行期间执行处理器的扫描测试。

公开(公告)号：US5507212A

公开(公告)日：1996-04-16

申请号：US181003

申请日：1994-01-14

申请人： Gary Morrison

发明人： Gary Morrison

IPC分类号： B23D57/00 ,  B25H7/04 ,  B26F1/38 ,  B28D1/22 ,  C03B33/12 ,  B26D3/08 ,  C03B33/10

CPC分类号： C03B33/12 ,  B23D57/0076 ,  B25H7/04 ,  B26F1/3846 ,  B28D1/225 ,  Y10T83/0333 ,  Y10T83/853 ,  Y10T83/8749

摘要： A radial arm saw glass cutting attachment including an arm having an orthogonal and a radially oriented glass cutter. The arm attaches to the radial arm saw blade attachment shaft and the shaft is oriented orthogonally to a glass plate being prepared for cutting for the purpose of producing circular or annular cut patterns, or the shaft is oriented parallel to the plane of the glass plate for the purpose of producing linear and angularly disposed linear cuts. A graduated scale which enables setting radius or diameter of a cut circle, and a thumbscrew lock for the freely sliding orthogonal cutter are included.

摘要翻译： 一种径向臂锯玻璃切割附件，包括具有正交和径向取向的玻璃切割器的臂。 臂连接到径向臂锯片附接轴，并且轴正交于准备切割用于制造圆形或环形切割图案的玻璃板，或者轴平行于玻璃板的平面定向， 产生线性和角度设置的线性切割的目的。 包括切割圆的半径或直径的刻度，以及用于自由滑动的正交切割器的指旋螺钉锁。

公开(公告)号：US11623255B2

公开(公告)日：2023-04-11

申请号：US17505830

申请日：2021-10-20

申请人： Travis Duffus ,  Gary Morrison

发明人： Travis Duffus ,  Gary Morrison

IPC分类号： B08B9/043 ,  E03F9/00 ,  E03C1/30

摘要： The present invention relates generally to the field of pump cleaning and unclogging. More specifically, the present invention relates to a tool which allows a user to unclog and remove rags, cloth materials, debris, or other obstructions from submersible and master-station pumps. Further, the invention can be used either as a hand tool or as an attachment to a crane or other machine for power assisted pulling, unclogging, and removal of rags, cloth materials, debris, and other obstructions.