公开(公告)号：US09557764B2

公开(公告)日：2017-01-31

申请号：US14980362

申请日：2015-12-28

Applicant: MediaTek Inc.

Inventor： Chen-Feng Chiang ,  Kai-Hsin Chen ,  Ming-Shi Liou ,  Chih-Tsung Yao

IPC: G11C7/00 ,  G06F1/10 ,  G11C11/4076 ,  G11C11/4094 ,  G06F13/16 ,  G11C7/22 ,  G11C7/10

CPC classification number: G06F1/10 ,  G06F13/16 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4094

Abstract: A clock tree circuit Including a first clock source, generating a first signal, and a first tree circuit. The first clock tree circuit includes a first driving stage for receiving the first signal, a second driving stage, connected to the first driving stage, a third driving stage, connected to the second driving stage, and a metal connection element, coupled between different nodes of the third driving stage and configured as a short-circuited element.

Abstract translation: 时钟树电路包括第一时钟源，产生第一信号和第一树电路。 第一时钟树电路包括用于接收第一信号的第一驱动级，连接到第一驱动级的第二驱动级，连接到第二驱动级的第三驱动级和耦合在不同节点之间的金属连接元件 并配置为短路元件。

公开(公告)号：US09627031B1

公开(公告)日：2017-04-18

申请号：US15067377

申请日：2016-03-11

Applicant: MediaTek Inc.

Inventor： Kai-Hsin Chen ,  Shih-Hsiu Lin

IPC: G11C7/00 ,  G11C11/4076 ,  G11C11/409 ,  G11C7/10 ,  G11C7/22 ,  G11C8/04

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/227 ,  G11C8/04 ,  G11C11/409 ,  G11C29/022 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/2254

Abstract: A control method for a memory system is provided. A memory controller of the memory system is configured to control the memory device. After a condition is met, the memory controller performs a retry operation to compensate for shifting of a data strobe signal sent from the memory device until the memory system enters a normal operation mode. When the shifting of the data strobe signal is compensated for, the number of pulses of the data strobe signal in the gating window is equal to the first predetermined number.

公开(公告)号：US09256245B2

公开(公告)日：2016-02-09

申请号：US14602562

申请日：2015-01-22

Applicant: MediaTek Inc.

Inventor： Chen-Feng Chiang ,  Kai-Hsin Chen ,  Ming-Shi Liou ,  Chih-Tsung Yao

IPC: G11C7/00 ,  G06F1/10 ,  G11C11/4076 ,  G11C11/4094

CPC classification number: G06F1/10 ,  G06F13/16 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4094

Abstract: A clock tree circuit includes a clock source and a tree circuit. The clock source generates a signal. The tree circuit at least includes five driving units and a metal connection element. A first driving unit has an input terminal for receiving the signal, and an output terminal coupled to a first node. A second driving unit has an input terminal coupled to the first node, and an output terminal coupled to a second node. A third driving unit has an input terminal coupled to the first node, and an output terminal coupled to a third node. A fourth driving unit has an input terminal coupled to the second node. A fifth driving unit has an input terminal coupled to the third node. The metal connection element is coupled between the second node and the third node, and configured as a short-circuited element.

Abstract translation: 时钟树电路包括时钟源和树电路。 时钟源产生一个信号。 树电路至少包括五个驱动单元和金属连接元件。 第一驱动单元具有用于接收信号的输入端子和耦合到第一节点的输出端子。 第二驱动单元具有耦合到第一节点的输入端子和耦合到第二节点的输出端子。 第三驱动单元具有耦合到第一节点的输入端子和耦合到第三节点的输出端子。 第四驱动单元具有耦合到第二节点的输入端子。 第五驱动单元具有耦合到第三节点的输入端。 金属连接元件耦合在第二节点和第三节点之间，并被配置为短路元件。