公开(公告)号：US11848646B2

公开(公告)日：2023-12-19

申请号：US17367616

申请日：2021-07-05

Applicant: MEDIATEK INC.

Inventor： Shih-Hsiung Chien ,  Sung-Han Wen ,  Kuan-Ta Chen

IPC: H03F3/04 ,  H03F3/45 ,  H03F1/02

CPC classification number: H03F1/0222 ,  H03F3/45636 ,  H03F1/0211 ,  H03F1/0244 ,  H03F2200/102

Abstract: An amplifier circuit includes a voltage-to-current conversion circuit and a current-to-voltage conversion circuit. The voltage-to-current conversion circuit generates a current signal according to an input voltage signal, and includes an operational transconductance amplifier (OTA) used to output the current signal at an output port of the OTA. The current-to-voltage conversion circuit generates an output voltage signal according to the current signal, and includes a linear amplifier (LA), wherein an input port of the LA is coupled to the output port of the OTA, and the output voltage signal is derived from an output signal at an output port of the LA.

公开(公告)号：US11025204B2

公开(公告)日：2021-06-01

申请号：US16149145

申请日：2018-10-02

Applicant: MEDIATEK INC.

Inventor： Ying-Wei Chou ,  Sung-Han Wen ,  Chen-Chien Lin ,  Jou Lee

IPC: H04B15/00 ,  H03F1/34 ,  H03H7/06 ,  H03F3/181 ,  H04R3/04 ,  H03G5/12 ,  H03F3/187 ,  H03F3/45

Abstract: The present invention provides a circuit having a filter with an amplifier circuit for filtering and amplifying an input signal to generate an output signal, wherein a corner frequency of the filter is adjustable to control a settling time of the output signal.

公开(公告)号：US10535651B2

公开(公告)日：2020-01-14

申请号：US15953772

申请日：2018-04-16

Applicant: MEDIATEK INC.

Inventor： Sung-Han Wen ,  Kuan-Ta Chen

IPC: H01L27/08 ,  H01L29/8605 ,  H01L49/02 ,  H01C10/14 ,  H03F3/45

Abstract: An impedance circuit includes a first poly-resistor and a second poly-resistor. The first poly-resistor has a first terminal coupled to a first node, and a second terminal coupled to a second node. The second poly-resistor has a first terminal coupled to the first node, and a second terminal coupled to the second node. The resistance between the first terminal and the second terminal of the first poly-resistor is determined according to a first control voltage. The resistance between the first terminal and the second terminal of the second poly-resistor is determined according to a second control voltage. The first control voltage and the second control voltage are determined according to a first voltage at the first node and a second voltage at the second node.

公开(公告)号：US20190166566A1

公开(公告)日：2019-05-30

申请号：US16121644

申请日：2018-09-05

Applicant: MEDIATEK INC.

Inventor： Sung-Han Wen ,  Ya-Chi Chen

IPC: H04W52/52 ,  H03F1/02 ,  H03F1/32 ,  H03F3/217

Abstract: The present invention provides an amplifier circuit, wherein the amplifier circuit includes a DAC, an output stage and a detector. In the operations of the amplifier circuit, the DAC is arranged for performing a digital-to-analog converting operation upon a digital input signal to generate an analog signal, the output stage is arranged for receiving the analog signal to generate an output signal, and the detector is arranged for detecting a characteristic of the input signal, and referring to the characteristic of the input signal to generate at least one control signal to adjust the output stage at a zero-crossing point of the output signal.

公开(公告)号：US20180124512A1

公开(公告)日：2018-05-03

申请号：US15853745

申请日：2017-12-23

Applicant: MediaTek Inc.

Inventor： Sung-Han Wen ,  Yu-Cheng Chang ,  Kuan-Ta Chen

IPC: H04R3/00 ,  H04B3/32

CPC classification number: H04R3/007 ,  H04B3/32 ,  H04R1/1041 ,  H04R5/04 ,  H04R29/001 ,  H04R2420/09

Abstract: A device for removing crosstalk includes a jack to form an electrical connection with a plug, and an audio unit to provide a left audio channel and a right audio channel to the plug. The audio unit includes a crosstalk cancellation circuit. The crosstalk cancellation circuit estimates the crosstalk between the left audio channel and the right audio channel to obtain an estimated right-to-left crosstalk and an estimated left-to-right crosstalk, and to remove the crosstalk by subtracting the estimated right-to-left crosstalk and the estimated left-to-right crosstalk from digital signals in the left audio channel and the right audio channel, respectively.

公开(公告)号：US20170150258A1

公开(公告)日：2017-05-25

申请号：US15232802

申请日：2016-08-09

Applicant: MediaTek Inc.

Inventor： Sung-Han Wen ,  Yu-Cheng Chang ,  Kuan-Ta Chen

IPC: H04R3/00 ,  H04B3/32

CPC classification number: H04R3/007 ,  H04B3/32 ,  H04R1/1041 ,  H04R5/04 ,  H04R29/001 ,  H04R2420/09

Abstract: A device includes an audio unit to provide a left audio channel, a right audio channel and a microphone channel to a headset plug. The device also includes a headset jack to form an electrical connection with the headset plug, and a swap switch configurable to swap connections of a ground terminal and a microphone terminal of the headset plug to the audio unit. The audio unit further includes: a first crosstalk cancellation circuit to subtract an estimated right-to-left crosstalk from a left digital path of the left audio channel, and to subtract an estimated left-to-right crosstalk from a right digital path of the right audio channel; and a second crosstalk cancellation circuit to subtract an estimated left-to-microphone crosstalk and an estimated right-to-microphone crosstalk from a microphone digital path of the microphone channel.

公开(公告)号：US20250080128A1

公开(公告)日：2025-03-06

申请号：US18822479

申请日：2024-09-03

Applicant: MEDIATEK INC.

Inventor： SUJITH KUMAR BILLA ,  Sung-Han Wen

IPC: H03M1/08

Abstract: A DAC cell circuit includes: at least a DAC cell, including: a first MOSFET having a drain coupled to a first switch for receiving a first current and coupled to a second switch for generating a second current, a source coupled to ground, and a gate coupled to a first bias voltage; a capacitor coupled between the gate and the drain of the first MOSFET; and a dead-band switch coupled between the gate of the first MOSFET and the bias node. The dead-band switch is controlled by a signal which is periodic with respect to a frequency equal to an input data rate of the DAC cell, and the dead-band switch is open during a data transition.

公开(公告)号：US20230078955A1

公开(公告)日：2023-03-16

申请号：US17884589

申请日：2022-08-10

Applicant: MEDIATEK INC.

Inventor： Shih-Hsiung Chien ,  Sung-Han Wen ,  Kuan-Ta Chen

IPC: H03F3/04

Abstract: The present invention provides a linear amplifier including an amplifier stage, a DC-shifting stage, a compensation network and a power stage. The amplifier stage is configured to generate a first signal and a second signal. The DC-shifting stage is configured to adjust a DC voltage of the first signal and a DC voltage of the second signal to generate an adjusted first signal and an adjusted second signal. The compensation network is configured to generate a first driving signal and a second driving signal according to the first signal, the second signal, the adjusted first signal and the adjusted second signal. The power stage is configured to generate an output signal according to the first driving signal and the second driving signal.

公开(公告)号：US20230077479A1

公开(公告)日：2023-03-16

申请号：US17853945

申请日：2022-06-30

Applicant: MEDIATEK INC.

Inventor： Sung-Han Wen ,  Yu-Hung Lin ,  Shih-Hsiung Chien ,  Chi-Heng Chung

IPC: H03F3/21 ,  H03F3/393 ,  H03F3/16

Abstract: The present invention provides an amplifier including an input stage, an amplifier stage, a power stage and a de-gain stage. The input stage is configured to receive an input signal to generate an amplified signal. The amplifier stage is configured to generate a first driving signal and a second driving signal according to the amplified signal. The power stage comprises a first input terminal and a second input terminal, wherein the power stage is coupled to a supply voltage and a ground voltage, for receiving the first driving signal and the second driving signal from the first input terminal and the second input terminal, respectively, and generating an output signal.

公开(公告)号：US11309839B2

公开(公告)日：2022-04-19

申请号：US16793226

申请日：2020-02-18

Applicant: MEDIATEK INC.

Inventor： Sung-Han Wen ,  Kuan-Ta Chen

IPC: H03F3/19 ,  H03F1/02 ,  H03F3/04 ,  H03G3/30

Abstract: A multi-stage amplifier with a high signal-to-noise ratio is introduced. Multiple amplification stages are cascaded between an input terminal and an output terminal of the amplifier. A controller switches the output stage among the multiple amplification stages from a normal mode to an attenuation mode in response to the amplifier input being lower than the threshold. In the attenuation mode, the output stage provides an attenuation resistor coupled in series with the load resistor of the amplifier. Noise is successfully attenuated by the attenuation-mode output stage.