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公开(公告)号：US20110320862A1
公开(公告)日：2011-12-29
申请号：US12822367
申请日：2010-06-24
申请人： Michael Blake , Timothy C. Bronson , Hieu T. Huynh , Pak-kin Mak
发明人： Michael Blake , Timothy C. Bronson , Hieu T. Huynh , Pak-kin Mak
CPC分类号： G11C29/08 , G06F11/1666 , G06F11/20 , G11C11/401 , G11C29/883 , G11C2029/0401
摘要： Embedded dynamic random access memory (EDRAM) macro disablement in a cache memory includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows, iteratively testing each line of the EDRAM macro, the testing including attempting at least one write operation at each line of the EDRAM macro, determining if an error occurred during the testing, and disabling write operations for an entire row of EDRAM macros associated with the EDRAM macro based on the determining.
摘要翻译： 高速缓冲存储器中的嵌入式动态随机存取存储器（EDRAM）宏禁用包括隔离高速缓存存储体的EDRAM宏，高速缓存存储体被划分成多个EDRAM宏的至少三行，所述EDRAM宏与一个 至少三行，迭代地测试EDRAM宏的每一行，测试包括尝试在EDRAM宏的每一行进行至少一次写操作，确定在测试期间是否发生错误，以及禁止整行的写操作 的基于确定的EDRAM宏相关联的EDRAM宏。
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公开(公告)号：US08990507B2
公开(公告)日：2015-03-24
申请号：US13495383
申请日：2012-06-13
申请人： Michael A. Blake , Pak-Kin Mak , Timothy C. Bronson , Hieu T. Huynh , Kenneth D. Klapproth , Vesselina K. Papazova
发明人： Michael A. Blake , Pak-Kin Mak , Timothy C. Bronson , Hieu T. Huynh , Kenneth D. Klapproth , Vesselina K. Papazova
CPC分类号： G06F12/0895 , G06F12/0804 , G06F12/0817 , G06F12/0891 , G06F12/128
摘要： Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where access to the cache directory is given a lower priority than other cache operations. It is determined that a specific directory entry in the cache directory has a change line state that indicates it is modified. A store operation is performed to send a copy of the specific corresponding cache entry to the system memory as part of a cache management function. The specific directory entry is updated to indicate that the change line state is unmodified.
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公开(公告)号：US20130339613A1
公开(公告)日：2013-12-19
申请号：US13495383
申请日：2012-06-13
申请人： Michael A. Blake , Pak-Kin Mak , Timothy C. Bronson , Hieu T. Huynh , Kenneth D. Klapproth , Vesselina K. Papazova
发明人： Michael A. Blake , Pak-Kin Mak , Timothy C. Bronson , Hieu T. Huynh , Kenneth D. Klapproth , Vesselina K. Papazova
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F12/0804 , G06F12/0817 , G06F12/0891 , G06F12/128
摘要： Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where access to the cache directory is given a lower priority than other cache operations. It is determined that a specific directory entry in the cache directory has a change line state that indicates it is modified. A store operation is performed to send a copy of the specific corresponding cache entry to the system memory as part of a cache management function. The specific directory entry is updated to indicate that the change line state is unmodified.
摘要翻译： 实施例涉及将数据存储到系统存储器。 一个方面包括通过步进引擎访问具有多个目录条目的高速缓存目录的连续条目，其中对高速缓存目录的访问被给予比其他高速缓存操作更低的优先级。 确定高速缓存目录中的特定目录条目具有指示其被修改的改变行状态。 执行存储操作以将特定对应的高速缓存条目的副本作为高速缓存管理功能的一部分发送到系统存储器。 特定目录条目被更新以指示改变线状态是未修改的。
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公开(公告)号：US08381019B2
公开(公告)日：2013-02-19
申请号：US12822367
申请日：2010-06-24
IPC分类号： G06F11/00
CPC分类号： G11C29/08 , G06F11/1666 , G06F11/20 , G11C11/401 , G11C29/883 , G11C2029/0401
摘要： Embedded dynamic random access memory (EDRAM) macro disablement in a cache memory includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows, iteratively testing each line of the EDRAM macro, the testing including attempting at least one write operation at each line of the EDRAM macro, determining if an error occurred during the testing, and disabling write operations for an entire row of EDRAM macros associated with the EDRAM macro based on the determining.
摘要翻译： 高速缓冲存储器中的嵌入式动态随机存取存储器（EDRAM）宏禁用包括隔离高速缓存存储体的EDRAM宏，高速缓存存储体被划分成多个EDRAM宏的至少三行，所述EDRAM宏与一个 至少三行，迭代地测试EDRAM宏的每一行，测试包括尝试在EDRAM宏的每一行进行至少一次写操作，确定在测试期间是否发生错误，以及禁止整行的写操作 的基于确定的EDRAM宏相关联的EDRAM宏。
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公开(公告)号：US20110320700A1
公开(公告)日：2011-12-29
申请号：US12822364
申请日：2010-06-24
IPC分类号： G06F12/06
CPC分类号： G06F12/0846 , G06F12/0893
摘要： Concurrent refresh in a cache memory includes calculating a refresh time interval at a centralized refresh controller, the centralized refresh controller being common to all cache memory banks of the cache memory, transmitting a starting time of the refresh time interval to a bank controller, the bank controller being local to, and associated with, only one cache memory bank of the cache memory, sampling a continuous refresh status indicative of a number of refreshes necessary to maintain data within the cache memory bank associated with the bank controller, requesting a gap in a processing pipeline of the cache memory to facilitate the number of refreshes necessary, receiving a refresh grant in response to the requesting, and transmitting an encoded refresh command to the bank controller, the encoded refresh command indicating a number of refresh operations granted to the cache memory bank associated with the bank controller.
摘要翻译： 高速缓冲存储器中的并发刷新包括计算集中式刷新控制器的刷新时间间隔，集中式刷新控制器对于高速缓存存储器的所有高速缓存存储体共同，将刷新时间间隔的开始时间发送到银行控制器，银行 控制器本身并且仅与高速缓冲存储器的一个高速缓冲存储器组相关联，并且对与表示控制器相关联的高速缓存存储器中的数据进行维护所需的刷新次数的连续刷新状态进行采样，请求在 处理高速缓冲存储器的流水线以便于所需的刷新次数，响应于请求接收刷新许可，并向编组控制器发送编码的刷新命令，编码的刷新命令指示授予高速缓冲存储器的刷新操作的次数 与银行控制人有关的银行。
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6.发明授权Dynamic cache correction mechanism to allow constant access to addressable index 失效动态高速缓存校正机制，允许持续访问可寻址索引公开(公告)号：US08719618B2
公开(公告)日：2014-05-06
申请号：US13495174
申请日：2012-06-13
IPC分类号： G06F11/00
CPC分类号： G06F11/073 , G06F11/0757 , G06F11/20 , G06F12/08 , G06F12/0811 , G06F12/0864 , G06F12/126 , G06F2212/1032
摘要： A technique is provided for a cache. A cache controller accesses a set in a congruence class and determines that the set contains corrupted data based on an error being found. The cache controller determines that a delete parameter for taking the set offline is met and determines that a number of currently offline sets in the congruence class is higher than an allowable offline number threshold. The cache controller determines not to take the set in which the error was found offline based on determining that the number of currently offline sets in the congruence class is higher than the allowable offline number threshold.
摘要翻译： 为缓存提供了一种技术。 高速缓存控制器访问同余类中的集合，并根据发现的错误确定该集合包含损坏的数据。 高速缓存控制器确定满足设置离线的删除参数，并确定同余类中当前离线集合的数量高于允许的离线号码阈值。 缓存控制器根据确定同余类中当前离线集合的数量高于允许的离线号码阈值，确定不采取脱机发生的集合。
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7.发明申请DYNAMIC CACHE CORRECTION MECHANISM TO ALLOW CONSTANT ACCESS TO ADDRESSABLE INDEX 失效动态缓存机制可以持续访问可寻址索引公开(公告)号：US20130339785A1
公开(公告)日：2013-12-19
申请号：US13495174
申请日：2012-06-13
IPC分类号： G06F11/20
CPC分类号： G06F11/073 , G06F11/0757 , G06F11/20 , G06F12/08 , G06F12/0811 , G06F12/0864 , G06F12/126 , G06F2212/1032
摘要： A technique is provided for a cache. A cache controller accesses a set in a congruence class and determines that the set contains corrupted data based on an error being found. The cache controller determines that a delete parameter for taking the set offline is met and determines that a number of currently offline sets in the congruence class is higher than an allowable offline number threshold. The cache controller determines not to take the set in which the error was found offline based on determining that the number of currently offline sets in the congruence class is higher than the allowable offline number threshold.
摘要翻译： 为缓存提供了一种技术。 高速缓存控制器访问同余类中的集合，并根据发现的错误确定该集合包含损坏的数据。 高速缓存控制器确定满足设置离线的删除参数，并确定同余类中当前离线集合的数量高于允许的离线号码阈值。 缓存控制器根据确定同余类中当前离线集合的数量高于允许的离线号码阈值，确定不采取脱机发生的集合。
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公开(公告)号：US08458405B2
公开(公告)日：2013-06-04
申请号：US12821891
申请日：2010-06-23
CPC分类号： G06F12/0895
摘要： Various embodiments of the present invention manage access to a cache memory. In one embodiment, a set of cache bank availability vectors are generated based on a current set of cache access requests currently operating on a set of cache banks and at least a variable busy time of a cache memory includes the set of cache banks. The set of cache bank availability vectors indicate an availability of the set of cache banks. A set of cache access requests for accessing a set of given cache banks within the set of cache banks is received. At least one cache access request in the set of cache access requests is selected to access a given cache bank based on the a cache bank availability vectors associated with the given cache bank and the set of access request parameters associated with the at least one cache access that has been selected.
摘要翻译： 本发明的各种实施例管理对高速缓冲存储器的访问。 在一个实施例中，基于当前在一组高速缓存组上操作的当前高速缓存访问请求集合来生成一组高速缓存存储库可用性向量，并且至少高速缓冲存储器的可变繁忙时间包括该组缓存存储体。 该组缓存库可用性向量指示该组缓存存储体的可用性。 接收用于访问该组缓存组内的一组给定高速缓存存储体的一组缓存访问请求。 选择该组高速缓存访问请求中的至少一个高速缓存访问请求以基于与给定高速缓存组相关联的高速缓存存储体可用性向量和与该至少一个高速缓存访问相关联的一组访问请求参数访问给定高速缓存组 已被选中。
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公开(公告)号：US08291157B2
公开(公告)日：2012-10-16
申请号：US12822364
申请日：2010-06-24
IPC分类号： G06F12/00
CPC分类号： G06F12/0846 , G06F12/0893
摘要： Concurrent refresh in a cache memory includes calculating a refresh time interval at a centralized refresh controller, the centralized refresh controller being common to all cache memory banks of the cache memory, transmitting a starting time of the refresh time interval to a bank controller, the bank controller being local to, and associated with, only one cache memory bank of the cache memory, sampling a continuous refresh status indicative of a number of refreshes necessary to maintain data within the cache memory bank associated with the bank controller, requesting a gap in a processing pipeline of the cache memory to facilitate the number of refreshes necessary, receiving a refresh grant in response to the requesting, and transmitting an encoded refresh command to the bank controller, the encoded refresh command indicating a number of refresh operations granted to the cache memory bank associated with the bank controller.
摘要翻译： 高速缓冲存储器中的并发刷新包括计算集中式刷新控制器的刷新时间间隔，集中式刷新控制器对于高速缓存存储器的所有高速缓存存储体共同，将刷新时间间隔的开始时间发送到银行控制器，银行 控制器本身并且仅与高速缓冲存储器的一个高速缓冲存储器组相关联，并且对与表示控制器相关联的高速缓存存储器中的数据进行维护所需的刷新次数的连续刷新状态进行采样，请求在 处理高速缓冲存储器的流水线以便于所需的刷新次数，响应于请求接收刷新许可，并向编组控制器发送编码的刷新命令，编码的刷新命令指示授予高速缓冲存储器的刷新操作的次数 与银行控制人有关的银行。
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公开(公告)号：US20110320729A1
公开(公告)日：2011-12-29
申请号：US12821891
申请日：2010-06-23
CPC分类号： G06F12/0895
摘要： Various embodiments of the present invention manage access to a cache memory. In one embodiment, a set of cache bank availability vectors are generated based on a current set of cache access requests currently operating on a set of cache banks and at least a variable busy time of a cache memory includes the set of cache banks. The set of cache bank availability vectors indicate an availability of the set of cache banks. A set of cache access requests for accessing a set of given cache banks within the set of cache banks is received. At least one cache access request in the set of cache access requests is selected to access a given cache bank based on the a cache bank availability vectors associated with the given cache bank and the set of access request parameters associated with the at least one cache access that has been selected.
摘要翻译： 本发明的各种实施例管理对高速缓冲存储器的访问。 在一个实施例中，基于当前在一组高速缓存组上操作的当前高速缓存访问请求集合来生成一组高速缓存存储库可用性向量，并且至少高速缓存存储器的可变繁忙时间包括该组高速缓冲存储器组。 该组缓存库可用性向量指示该组缓存存储体的可用性。 接收用于访问该组缓存组内的一组给定高速缓存存储体的一组缓存访问请求。 选择该组高速缓存访问请求中的至少一个高速缓存访问请求以基于与给定高速缓存组相关联的高速缓存存储体可用性向量和与该至少一个高速缓存访问相关联的一组访问请求参数访问给定高速缓存组 已被选中。
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