公开(公告)号：US20110320862A1

公开(公告)日：2011-12-29

申请号：US12822367

申请日：2010-06-24

申请人： Michael Blake ,  Timothy C. Bronson ,  Hieu T. Huynh ,  Pak-kin Mak

发明人： Michael Blake ,  Timothy C. Bronson ,  Hieu T. Huynh ,  Pak-kin Mak

IPC分类号： G06F11/27 ,  G06F11/20 ,  G06F11/00

CPC分类号： G11C29/08 ,  G06F11/1666 ,  G06F11/20 ,  G11C11/401 ,  G11C29/883 ,  G11C2029/0401

摘要： Embedded dynamic random access memory (EDRAM) macro disablement in a cache memory includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows, iteratively testing each line of the EDRAM macro, the testing including attempting at least one write operation at each line of the EDRAM macro, determining if an error occurred during the testing, and disabling write operations for an entire row of EDRAM macros associated with the EDRAM macro based on the determining.

摘要翻译： 高速缓冲存储器中的嵌入式动态随机存取存储器（EDRAM）宏禁用包括隔离高速缓存存储体的EDRAM宏，高速缓存存储体被划分成多个EDRAM宏的至少三行，所述EDRAM宏与一个 至少三行，迭代地测试EDRAM宏的每一行，测试包括尝试在EDRAM宏的每一行进行至少一次写操作，确定在测试期间是否发生错误，以及禁止整行的写操作 的基于确定的EDRAM宏相关联的EDRAM宏。

公开(公告)号：US20060184750A1

公开(公告)日：2006-08-17

申请号：US11402599

申请日：2006-04-12

申请人： Michael Blake ,  Pak-kin Mak ,  Adrian Seigler ,  Gary VanHuben

发明人： Michael Blake ,  Pak-kin Mak ,  Adrian Seigler ,  Gary VanHuben

IPC分类号： G06F12/00

CPC分类号： G06F12/0813 ,  G06F12/0831

摘要： A shared memory symmetrical processing system including a plurality of nodes each having a system control element for routing internodal communications. A first ring and a second ring interconnect the plurality of nodes, wherein data in said first ring flows in opposite directions with respect to said second ring. A receiver receives a plurality of incoming messages via the first or second ring and merges a plurality of incoming message responses with a local outgoing message response to provide a merged response. Each of the plurality of nodes includes any combination of the following: at least one processor, cache memory, a plurality of I/O adapters, and main memory. The system control element includes a plurality of controllers for maintaining coherency in the system.

摘要翻译： 一种共享存储器对称处理系统，包括多个节点，每个节点具有用于路由节点间通信的系统控制元件。 第一环和第二环互连多个节点，其中所述第一环中的数据相对于所述第二环相反的方向流动。 接收器经由第一或第二环接收多个传入消息，并将多个传入消息响应与本地传出消息响应合并以提供合并响应。 多个节点中的每一个包括以下的任何组合：至少一个处理器，高速缓冲存储器，多个I / O适配器和主存储器。 系统控制元件包括用于维持系统中一致性的多个控制器。

公开(公告)号：US09003125B2

公开(公告)日：2015-04-07

申请号：US13523535

申请日：2012-06-14

申请人： Ekaterina M. Ambroladze ,  Michael Blake ,  Tim Bronson ,  Garrett Drapala ,  Pak-kin Mak ,  Arthur J. O'Neill

发明人： Ekaterina M. Ambroladze ,  Michael Blake ,  Tim Bronson ,  Garrett Drapala ,  Pak-kin Mak ,  Arthur J. O'Neill

IPC分类号： G06F12/08

CPC分类号： G06F12/0891 ,  G06F12/0815 ,  G06F12/0859

摘要： A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.

摘要翻译： 提供了高速缓存一致性技术。 高速缓存控制器基于第一事务的高速缓存未命中从一个等同类中的多个集合中选择第一集合，并且将锁定放置在整个一致类中，其中锁定防止其他事务访问同余类。 高速缓存控制器在高速缓存目录中指定具有指示第一事务在第一集合上工作的标记位的第一集合，并且第一集合的标记位阻止其他事务访问同余类中的第一集合。 高速缓存控制器基于为第一组指定的标记位移除同余类上的锁，并且基于在一致类中的第一集合上的第一次交易完成工作将第一组的标记位重置为未标记位 。

公开(公告)号：US20130339622A1

公开(公告)日：2013-12-19

申请号：US13523535

申请日：2012-06-14

申请人： Ekaterina M. Ambroladze ,  Michael Blake ,  Tim Bronson ,  Garrett Drapala ,  Pak-kin Mak ,  Arthur J. O'Neill

发明人： Ekaterina M. Ambroladze ,  Michael Blake ,  Tim Bronson ,  Garrett Drapala ,  Pak-kin Mak ,  Arthur J. O'Neill

IPC分类号： G06F12/08

CPC分类号： G06F12/0891 ,  G06F12/0815 ,  G06F12/0859

摘要： A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.

摘要翻译： 提供了高速缓存一致性技术。 高速缓存控制器基于第一事务的高速缓存未命中从一个等同类中的多个集合中选择第一集合，并且将锁定放置在整个一致类中，其中锁定防止其他事务访问同余类。 高速缓存控制器在高速缓存目录中指定具有指示第一事务在第一集合上工作的标记位的第一集合，并且第一集合的标记位阻止其他事务访问同余类中的第一集合。 高速缓存控制器基于为第一组指定的标记位移除同余类上的锁，并且基于在一致类中的第一集合上的第一次交易完成工作将第一组的标记位重置为未标记位 。

公开(公告)号：US20070222250A1

公开(公告)日：2007-09-27

申请号：US11386525

申请日：2006-03-22

申请人： Michael Miller ,  Brian Baibak ,  Brent Everett ,  Craig Smith ,  Michael Blake

发明人： Michael Miller ,  Brian Baibak ,  Brent Everett ,  Craig Smith ,  Michael Blake

IPC分类号： B60N2/04

CPC分类号： B60N2/01583 ,  B60N2205/20

摘要： A vehicle seat latch (24) includes a latch member (40) and a blocking member (70) that each have associated first and second blocking surfaces (80, 82 and 88, 90) for holding the latch member in a latched position with the blocking member in a blocking position. The first blocking surfaces (80 and 88) of the latch member and blocking member have a pressure angle between 4.6 and 6.6 degrees while the second blocking surfaces (82 and 90) have a zero degree pressure angle and are slightly spaced from each other. A deformable blocking portion (84) of the blocking member (70) defines its first blocking surface (88) and is deformed by excessive loading so that the zero degree pressure angle second blocking surfaces (82 and 90) then contact each other to hold the latch member in its latched position.

摘要翻译： 车辆座椅闩锁（24）包括闩锁构件（40）和阻挡构件（70），每个阻挡构件具有相关联的第一和第二阻挡表面（80,82和88,90），用于将闩锁构件保持在闩锁位置， 阻挡构件处于阻挡位置。 闩锁构件和阻挡构件的第一阻挡表面（80和88）具有在4.6和6.6度之间的压力角，而第二阻挡表面（82和90）具有零压力角并且彼此稍微间隔开。 阻挡构件（70）的可变形阻挡部分（84）限定其第一阻挡表面（88）并且由于过大的载荷而变形，使得零压力角第二阻挡表面（82和90）然后彼此接触以保持 闩锁构件处于其锁定位置。

公开(公告)号：US20070181475A1

公开(公告)日：2007-08-09

申请号：US11348445

申请日：2006-02-07

申请人： Michael Blake

发明人： Michael Blake

IPC分类号： E04H4/16

CPC分类号： E04H4/1254

摘要： A leaf and debris catcher for removing leaves and/or debris from a body of water. In one aspect of the invention, the leaf and debris catcher includes a base, a first vertical support member, a horizontal support member, a second vertical support member, and a leaf and debris collection member. In another aspect of the invention, a method is provided for removing leaves from a body of water. The method includes the steps of: providing a leaf and debris collection member; positioning the leaf and debris collection member in a body of water such that the leaf and debris collection member is located in a flow of water; collecting leaves in the leaf and debris collection member; removing the leaf and debris collection member from the flow of water; and removing leaves from the leaf and debris collection member.

摘要翻译： 用于从水体中除去叶子和/或碎屑的叶子和碎屑捕集器。 在本发明的一个方面，叶片和碎片捕集器包括基座，第一垂直支撑构件，水平支撑构件，第二垂直支撑构件以及叶片和碎片收集构件。 在本发明的另一方面，提供了一种从水体中除去叶子的方法。 该方法包括以下步骤：提供叶片和碎片收集构件; 将叶片和碎片收集构件定位在水体中，使得叶片和碎片收集构件位于水流中; 收集叶片和碎片收集部件中的叶子; 从水流中除去叶片和碎片收集构件; 并从叶片和碎片收集构件上除去叶子。

公开(公告)号：US20160367157A1

公开(公告)日：2016-12-22

申请号：US15004345

申请日：2016-01-22

申请人： Michael Blake ,  Rodney Kugizaki

发明人： Michael Blake ,  Rodney Kugizaki

IPC分类号： A61B5/024 ,  A61B5/0452 ,  A61B5/0205 ,  A61B5/053 ,  A61B5/021 ,  A61B5/0456 ,  A61B5/00 ,  A61B5/11 ,  A61B5/0408 ,  A61B5/08

CPC分类号： A61B5/02405 ,  A61B5/02055 ,  A61B5/021 ,  A61B5/04085 ,  A61B5/0428 ,  A61B5/0452 ,  A61B5/0456 ,  A61B5/0468 ,  A61B5/053 ,  A61B5/08 ,  A61B5/1118 ,  A61B5/6823 ,  A61B5/6831

摘要： Methods, devices, and systems for monitoring heart rate variability (HRV). The HRV monitoring systems and devices are adapted to give immediate feedback to the subject concerning their current condition and any pertinent changes in their condition. The HRV monitoring systems and devices detect, analyze, and assess HRV against a pre-determined application or user need. They also have the ability to provide real time notifications based on the system's assessment of a user's heart HRV and changes in the HRV.

摘要翻译： 用于监测心率变异性（HRV）的方法，装置和系统。 HRV监测系统和设备适于立即向受试者反馈其当前状况及其状况的任何相关变化。 HRV监控系统和设备根据预定应用或用户需求检测，分析和评估HRV。 他们还能够根据系统对用户心脏HRV和HRV变化的评估来提供实时通知。

公开(公告)号：US20070124999A1

公开(公告)日：2007-06-07

申请号：US11537088

申请日：2006-09-29

申请人： Michael Blake ,  Raymond Blake

发明人： Michael Blake ,  Raymond Blake

IPC分类号： E05D15/22

CPC分类号： E04G21/30 ,  G09F19/22

摘要： A door wrap including two piece door surface cover connected by a middle jointing section for attachment to a door to protect both sides or top edge of the door on which it is mounted. The door wrap not only protects the door, but also allows the door to be fully functional, such as to be opened, closed or locked. The two-piece door surface covers of the door wrap may be constructed from a piece or pieces of cardboard material while the middle joining section may be made of plastic material. The door wrap may be custom made for uniquely mounted or sized doors, or assembled in standard sizes to fit most doors.

摘要翻译： 一个门包装，包括两个门面盖，通过中间接合部分连接，用于连接到门以保护安装在其上的门的两侧或顶部边缘。 门罩不仅保护门，而且还允许门完全起作用，例如打开，关闭或锁定。 门包装件的两件式门表面盖可以由一块或多块纸板材料构成，而中间连接部分可以由塑料材料制成。 门包装可以定制为独特的安装或尺寸的门，或组装成标准尺寸以适合大多数门。

公开(公告)号：US20050076147A1

公开(公告)日：2005-04-07

申请号：US10668131

申请日：2003-09-24

申请人： Michael Blake ,  Christopher Wiencek

发明人： Michael Blake ,  Christopher Wiencek

IPC分类号： H04L12/46 ,  H04L29/06 ,  G06F15/173 ,  G06F15/16

CPC分类号： H04L12/4641 ,  H04L69/22

摘要： An interface controller that connects devices which read and write the NMEA 0183 sentence data in a RS422 electrical format, to the Ethernet for transmission. NMEA 0183 sentence data is encapsulated and routed to other interface controllers, and/or to user applications operating on computers. A software interface utility designed to operate on the same computer as the users application programs will provide the transparency and the routing/mapping between the Ethernet transmitted NMEA 0183 sentence data and the users application programs communications interface, transparently.

摘要翻译： 一个接口控制器，用于将以RS422电格式读取和写入NMEA 0183句子数据的设备连接到以太网进行传输。 NMEA 0183句子数据被封装并路由到其他接口控制器和/或在计算机上操作的用户应用程序。 设计用于在与用户应用程序相同的计算机上操作的软件接口实用程序将透明地提供以太网传输的NMEA 0183句子数据与用户应用程序通信接口之间的透明度和路由/映射。

公开(公告)号：US20110320699A1

公开(公告)日：2011-12-29

申请号：US12822361

申请日：2010-06-24

申请人： Michael Blake ,  Timothy Bronson ,  Hieu Huynh ,  Kenneth D. Klapproth

发明人： Michael Blake ,  Timothy Bronson ,  Hieu Huynh ,  Kenneth D. Klapproth

IPC分类号： G06F12/08 ,  G06F1/04 ,  G06F12/00

CPC分类号： G06F12/0897 ,  G06F13/14 ,  G06F13/16 ,  G06F13/1605 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40607 ,  G11C11/40618

摘要： System refresh in a cache memory includes generating a refresh time period (RTIM) pulse at a centralized refresh controller of the cache memory, activating a refresh request at the centralized refresh controller in response to generating the RTIM pulse, the refresh request associated with a single cache memory bank of the cache memory, receiving a refresh grant in response to activating the refresh request, and transmitting the refresh grant to a bank controller, the bank controller associated, and localized, at the single cache memory bank of the cache memory.

摘要翻译： 高速缓冲存储器中的系统刷新包括在高速缓存存储器的集中式刷新控制器处产生刷新时间周期（RTIM）脉冲，响应于产生RTIM脉冲在集中式刷新控制器处激活刷新请求，刷新请求与单个 高速缓冲存储器的高速缓冲存储器组，响应于激活刷新请求而接收刷新许可，以及将刷新许可发送到在高速缓存存储器的单个高速缓冲存储器组处相关联并被本地化的存储体控制器。