公开(公告)号：US20150340435A1

公开(公告)日：2015-11-26

申请号：US14727768

申请日：2015-06-01

Applicant: Microchip Technology Inc.

Inventor： Benedict C.K. Choy ,  Ching Chu ,  Haibing (Robin) Liu ,  Ming-Yuan Yeh

IPC: H01L29/06 ,  H01L27/088 ,  H01L23/48 ,  H01L29/78

CPC classification number: H01L29/0642 ,  H01L23/481 ,  H01L23/49575 ,  H01L23/525 ,  H01L24/06 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L27/088 ,  H01L29/0878 ,  H01L29/66712 ,  H01L29/7809 ,  H01L29/7827 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48135 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A circuit module comprises a die attach pad with a surface and a plurality of leads surrounding the surface. A nonconductive adhesive is on the surface. A plurality of electronic circuit dies are on the surface of the die attach pad. Each die has a top surface and a bottom surface with the bottom surface on the adhesive. The top surface has a plurality of bonding pads. A first electronic circuit die has at least one routing path of a conductive material connecting a first bonding pad to a second bonding pad. A first bonding wire connects a bonding pad of a second electronic circuit die to the first bonding pad of the first electronic die. A second bonding wire connects the second bonding pad of the first electronic circuit die to a lead. Where one of the dies contains vertical circuit element, where a doped layer forms a terminal along the bottom surface of the layer, a trench filled with doped polysilicon extends from the top surface to the terminal to connect to the terminal. The doped polysilicon filled trench also serves to isolate and separate different circuit elements.

Abstract translation: 电路模块包括具有表面的管芯附接垫和围绕表面的多个引线。 非导电粘合剂在表面上。 多个电子电路管芯在管芯附着垫的表面上。 每个模具具有顶表面和底表面，底表面在粘合剂上。 顶表面具有多个接合焊盘。 第一电子电路管芯具有将第一接合焊盘连接到第二接合焊盘的导电材料的至少一个布线路径。 第一接合线将第二电子电路管芯的接合焊盘连接到第一电子管芯的第一接合焊盘。 第二接合线将第一电子电路管芯的第二接合焊盘连接到引线。 在其中一个裸片包含垂直电路元件的情况下，其中掺杂层沿着该层的底表面形成端子，填充有掺杂多晶硅的沟槽从顶表面延伸到端子以连接至端子。 掺杂多晶硅填充的沟槽还用于隔离和分离不同的电路元件。

公开(公告)号：US09975145B2

公开(公告)日：2018-05-22

申请号：US14045689

申请日：2013-10-03

Applicant: Microchip Technology Inc.

Inventor： Jimes Lei ,  Ching Chu

IPC: B06B1/02

CPC classification number: B06B1/0215

Abstract: An electrical waveform generating circuit has a pair of Pulse Amplitude Controlled Switching Current Sources (PACS). A gate pulse driver circuit is coupled to an input of each of the pair of PACS for sending gate pulses for driving the pair of PACS. A digital-to-analog converter (DAC) circuit is coupled to the gate pulse driver circuit for controlling amplitudes of the gate pulses. A transducer is coupled to the PACS.