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    Thrumold post package with reverse build up hybrid additive structure
    1.
    发明授权
    Thrumold post package with reverse build up hybrid additive structure 有权

    公开(公告)号：US10593568B2

    公开(公告)日：2020-03-17

    申请号：US16123158

    申请日：2018-09-06

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  John F. Kaeding ,  Ashok Pachamuthu ,  Mark E. Tuttle

    IPC: H01L21/56 ,  H01L23/31

    Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.

    METHODS OF MAKING SEMICONDUCTOR DEVICE MODULES WITH INCREASED YIELD
    3.
    发明申请
    METHODS OF MAKING SEMICONDUCTOR DEVICE MODULES WITH INCREASED YIELD 审中-公开

    公开(公告)号：US20190035755A1

    公开(公告)日：2019-01-31

    申请号：US15660442

    申请日：2017-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Ashok Pachamuthu ,  Chan H. Yoo ,  Szu-Ying Ho ,  John F. Kaeding

    IPC: H01L23/00 ,  H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L23/31

    Abstract: Methods of making semiconductor device modules may involve forming holes in a sacrificial material and placing an electrically conductive material in the holes. The sacrificial material may be removed to expose posts of the electrically conductive material. A stack of semiconductor dice may be placed between at least two of the posts after removing the sacrificial material, one of the semiconductor dice of the stack including an active surface facing in a direction opposite a direction in which another active surface of another of the semiconductor dice of the stack. The posts and the stack of semiconductor dice may be at least laterally encapsulated in an encapsulant. Bond pads of the one of the semiconductor dice may be electrically connected to corresponding posts after at least laterally encapsulating the posts and the stack of semiconductor dice.

    Thrumold post package with reverse build up hybrid additive structure
    4.
    发明授权
    Thrumold post package with reverse build up hybrid additive structure 有权

    公开(公告)号：US10103038B1

    公开(公告)日：2018-10-16

    申请号：US15685921

    申请日：2017-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  John F. Kaeding ,  Ashok Pachamuthu ,  Mark E. Tuttle

    IPC: H01L21/00 ,  H01L21/56 ,  H01L23/31

    Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.

    Device module having a plurality of dies electrically connected by posts
    5.
    发明授权
    Device module having a plurality of dies electrically connected by posts 有权

    公开(公告)号：US10325874B2

    公开(公告)日：2019-06-18

    申请号：US16175449

    申请日：2018-10-30

    Applicant: Micron Technology, Inc.

    Inventor： Ashok Pachamuthu ,  Chan H. Yoo ,  Szu-Ying Ho ,  John F. Kaeding

    IPC: H01L23/34 ,  H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00 ,  H01L21/768

    Abstract: Semiconductor device modules may include a redistribution layer and a first semiconductor die. A second semiconductor die may be located on the first semiconductor die. Posts may be located laterally adjacent to the first semiconductor die and the second semiconductor die. A first encapsulant may at least laterally surround the first semiconductor die, the second semiconductor die, and the posts. Electrical connectors may extend laterally from the posts, over the first encapsulant, to bond pads on a second active surface of the second semiconductor die. A protective material may cover the electrical connectors. A second encapsulant may be located over the protective material and the electrical connectors. The second encapsulant may be in direct contact with the first encapsulant, the electrical connectors, and the protective material. Conductive bumps may be connected to the redistribution layer on a side of the redistribution layer opposite the first semiconductor die.

    SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR DIES
    6.
    发明申请
    SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR DIES 审中-公开

    公开(公告)号：US20190067248A1

    公开(公告)日：2019-02-28

    申请号：US15686029

    申请日：2017-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Ashok Pachamuthu

    IPC: H01L25/065 ,  H01L25/00

    Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.

    HYBRID ADDITIVE STRUCTURE STACKABLE MEMORY DIE USING WIRE BOND
    7.
    发明申请
    HYBRID ADDITIVE STRUCTURE STACKABLE MEMORY DIE USING WIRE BOND 审中-公开

    公开(公告)号：US20190067034A1

    公开(公告)日：2019-02-28

    申请号：US15685940

    申请日：2017-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Ashok Pachamuthu ,  Chan H. Yoo ,  John F. Kaeding

    IPC: H01L21/48 ,  H01L23/48 ,  H01L23/50 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

    Abstract: Semiconductor devices with redistribution structures that do not include pre-formed substrates and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die attached to a redistribution structure and electrically coupled to the redistribution structure via a plurality of wire bonds. The semiconductor device can also include one or more second semiconductor dies stacked on the first semiconductor die, wherein one or more of the first and second semiconductor dies are electrically coupled to the redistribution structure via a plurality of wire bonds. The semiconductor device can also include a molded material over the first and/or second semiconductor dies and a surface of the redistribution structure.

    Semiconductor device having laterally offset stacked semiconductor dies
    8.
    发明授权
    Semiconductor device having laterally offset stacked semiconductor dies 有权

    公开(公告)号：US11037910B2

    公开(公告)日：2021-06-15

    申请号：US16933649

    申请日：2020-07-20

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Ashok Pachamuthu

    IPC: H01L25/065 ,  H01L25/00

    Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.

    SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR DIES
    9.
    发明申请
    SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR DIES 审中-公开

    公开(公告)号：US20200350293A1

    公开(公告)日：2020-11-05

    申请号：US16933649

    申请日：2020-07-20

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Ashok Pachamuthu

    IPC: H01L25/065 ,  H01L25/00

    Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.

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