公开(公告)号：US11563008B2

公开(公告)日：2023-01-24

申请号：US17194859

申请日：2021-03-08

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Vinay Nair ,  Devesh Dadhich Shreeram ,  Ashwin Panday ,  Kangle Li ,  Zhiqiang Xie ,  Silvia Borsari ,  Mohd Kamran Akhtar ,  Si-Woo Lee

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

公开(公告)号：US10978306B2

公开(公告)日：2021-04-13

申请号：US16369797

申请日：2019-03-29

Applicant: Micron Technology, Inc.

Inventor： Jerome A. Imonigie ,  Adriel Jebin Jacob Jebaraj ,  Brian J. Kerley ,  Sanjeev Sapra ,  Ashwin Panday

IPC: H01L21/306 ,  H01L49/02 ,  H01L21/311 ,  H01L27/108 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/302

Abstract: Methods, apparatuses, and systems related to forming a recess in a semiconductor structure are described. An example method includes etching the semiconductor structure using an elevated temperature dilution of acid and water. The method further includes etching the semiconductor structure using a room temperature wet etch of acid and water and a surface modification chemistry.

公开(公告)号：US20250159912A1

公开(公告)日：2025-05-15

申请号：US18909685

申请日：2024-10-08

Applicant: Micron Technology, Inc.

Inventor： Dojun Kim ,  Sanket S. Kelkar ,  An-Jen B. Cheng ,  Christopher W. Petz ,  Ryan J. Waskiewicz ,  Michael Mutch ,  Ashwin Panday ,  Sarah bull

IPC: H10D1/00 ,  H10D1/68

Abstract: An apparatus comprising one or more capacitors that comprise a bottom electrode, a high-k dielectric material, and a top electrode. The bottom electrode comprises an oxygen-doped titanium nitride material and one or more undoped titanium nitride materials. The oxygen-doped titanium nitride material is on sidewalls of the one or more undoped titanium nitride materials and the one or more undoped titanium nitride materials extending between sidewalls of the oxygen-doped titanium nitride material. Electronic devices and methods of forming an electronic device are also disclosed.

公开(公告)号：US20220285357A1

公开(公告)日：2022-09-08

申请号：US17194859

申请日：2021-03-08

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Vinay Nair ,  Devesh Dadhich Shreeram ,  Ashwin Panday ,  Kangle Li ,  Zhiqiang Xie ,  Silvia Borsari ,  Mohd Kamran Akhtar ,  Si-Woo Lee

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

公开(公告)号：US20240431095A1

公开(公告)日：2024-12-26

申请号：US18733586

申请日：2024-06-04

Applicant: Micron Technology, Inc.

Inventor： Yoshitaka Nakamura ,  Ashwin Panday ,  Iche Huang ,  Richard Beeler ,  Dojun Kim ,  Lane T. Cunningham ,  Adriel Jebin Jacob Jebaraj ,  Scott E. Sills

IPC: H10B12/00

Abstract: Methods, apparatuses, and systems related to a three-dimensional semiconductor device having a doped liner at least disposed between a capacitor and an access device. The doped liner may be configured to provide dopants that diffuse into a semiconductor path of the access device and improve an electrical connection between the access device and the capacitor.

公开(公告)号：US20240389302A1

公开(公告)日：2024-11-21

申请号：US18658787

申请日：2024-05-08

Applicant: Micron Technology, Inc.

Inventor： Jerome A. Imonigie ,  Chia Ying Lin ,  Davide Dorigo ,  Elisabeth Barr ,  Wan Rou Luo ,  Shi Han Wang ,  Sanjeev Sapra ,  Ashwin Panday ,  Vivek Yadav

IPC: H10B12/00

Abstract: Methods, systems, and devices for contact foot wet pullback with liner wet punch are described. A first etching operation may be performed on a stack of materials and a first insulative material to form a plurality of segments including contacts, the contacts formed from a first conductive material of the stack of materials and extending at least partially through the first insulative material. A first liner material may be deposited over the segments and the first insulative material, and a directional gas bias operation may be performed to transform a portion of the first liner material in contact with an extension of the contacts into a second liner material. A second etching operation may be performed to remove the second liner material and expose a surface of the extension, and a third etching operation may be performed remove at least a portion of the extension.

公开(公告)号：US20200312954A1

公开(公告)日：2020-10-01

申请号：US16369797

申请日：2019-03-29

Applicant: Micron Technology, Inc.

Inventor： Jerome A. Imonigie ,  Adriel Jebin Jacob Jebaraj ,  Brian J. Kerley ,  Sanjeev Sapra ,  Ashwin Panday

IPC: H01L49/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/108

Abstract: Methods, apparatuses, and systems related to forming a recess in a semiconductor structure are described. An example method includes etching the semiconductor structure using an elevated temperature dilution of acid and water. The method further includes etching the semiconductor structure using a room temperature wet etch of acid and water and a surface modification chemistry.