公开(公告)号：US20240282751A1

公开(公告)日：2024-08-22

申请号：US18440444

申请日：2024-02-13

Applicant: Micron Technology, Inc.

Inventor： Ling Pan ,  Seng Kim Ye ,  Kelvin Aik Boo Tan ,  Hong Wan Ng ,  See Hiong Leow ,  Chong C. Hui

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/48 ,  H01L2224/08146 ,  H01L2224/08225 ,  H01L2224/48132 ,  H01L2224/48147 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/182 ,  H01L2924/3511

Abstract: A variety of applications can include systems with packaged electronic devices having multiple dies arranged on a substrate with a downset design. A substrate with a downset design can include an upper portion and a lower portion with a downset portion connecting the upper portion to the lower portion. The downset portion can include through vias to provide conductive paths between the lower portion and the upper portion. Dies can be positioned with a region defined by walls of the downset portion with a non-conductive film covering the dies in the region defined by walls of the downset portion. Additional dies can be positioned on the non-conductive film and the upper portion of the substrate. A packaged electronic device having a substrate with a downset design can be implemented to raise the neutral axis of the packaged electronic device to near the top surface of the dies.