WIRE BONDING FOR STACKED MEMORY DIES
    1.
    发明公开

    公开(公告)号:US20240063168A1

    公开(公告)日:2024-02-22

    申请号:US17889170

    申请日:2022-08-16

    CPC classification number: H01L24/48 H01L27/1052 H01L2224/48105

    Abstract: Methods, systems, and devices for wire bonding for stacked memory dies are described. A memory system may include a stack of memory dies. As the stack grows to include more and more memory dies, the length of the wires coupling the memory dies with the control circuit may increase. Bonding multiple wires using an adhesive may increase a gap between neighboring wires coupled with the same memory die or different memory dies. For example, bonding one wire to a neighboring wire may pull one or both of the bonded wires away from their original placement, increasing a gap between the bonded wires and one or more neighboring wires. Bonding the wires coupled with a lower memory die may increase a gap such that sagging wires coupled with an upper memory die may be positioned in the gap to avoid shorting with the lower wires.

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