公开(公告)号：US20240282751A1

公开(公告)日：2024-08-22

申请号：US18440444

申请日：2024-02-13

申请人： Micron Technology, Inc.

发明人： Ling Pan ,  Seng Kim Ye ,  Kelvin Aik Boo Tan ,  Hong Wan Ng ,  See Hiong Leow ,  Chong C. Hui

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/48 ,  H01L2224/08146 ,  H01L2224/08225 ,  H01L2224/48132 ,  H01L2224/48147 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/182 ,  H01L2924/3511

摘要： A variety of applications can include systems with packaged electronic devices having multiple dies arranged on a substrate with a downset design. A substrate with a downset design can include an upper portion and a lower portion with a downset portion connecting the upper portion to the lower portion. The downset portion can include through vias to provide conductive paths between the lower portion and the upper portion. Dies can be positioned with a region defined by walls of the downset portion with a non-conductive film covering the dies in the region defined by walls of the downset portion. Additional dies can be positioned on the non-conductive film and the upper portion of the substrate. A packaged electronic device having a substrate with a downset design can be implemented to raise the neutral axis of the packaged electronic device to near the top surface of the dies.

公开(公告)号：US20240071980A1

公开(公告)日：2024-02-29

申请号：US17899550

申请日：2022-08-30

申请人： Micron Technology, Inc.

发明人： Kelvin Tan Aik Boo ,  Seng Kim Ye ,  Hong Wan Ng ,  Ling Pan ,  See Hiong Leow

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L24/48 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L23/49816 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48235 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/1434 ,  H01L2924/3512

摘要： Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having at least a first layer and a second layer, an interconnect extending through the package substrate, a stack of dies carried by the package substrate, and one or more wirebonds electrically coupling the stack of dies to package substrate. Each of the layers of the package substrate can include a section of the interconnect with a frustoconical shape. Each of the sections can be directly coupled together. Further, the section in an uppermost layer of the package substrate is exposed at an upper surface of the package substrate. The wirebonds can be directly coupled to the exposed surface of the uppermost section.

公开(公告)号：US20240057265A1

公开(公告)日：2024-02-15

申请号：US17885338

申请日：2022-08-10

申请人： Micron Technology, Inc.

发明人： Kelvin Tan Aik Boo ,  Ling Pan

IPC分类号： H05K3/34 ,  H05K1/02

CPC分类号： H05K3/3452 ,  H05K1/0271 ,  H05K3/3436 ,  H05K2201/099

摘要： Substrates having stress-releasing features, and associated systems and methods are disclosed herein. In some embodiments, the substrate includes a core layer, a metallization layer formed on an outer surface of the core layer, and a solder mask formed over the metallization layer and the outer surface. The metallization layer can include at least one bond pad and the solder mask can include a first opening exposing the bond pad. The first opening can be surrounded by a bonding region of the solder mask that thermally interfaces with the bond pad and/or any conductive structure bonded thereon. The solder mask can also include one or more second openings adjacent the first opening. Each of the second openings provides space for the solder mask to expand into to release stress due to thermal expansions of the bond pad, the solder mask, and/or the conductive structure during manufacturing and/or operation.

公开(公告)号：US20240304598A1

公开(公告)日：2024-09-12

申请号：US18424693

申请日：2024-01-26

申请人： Micron Technology, Inc.

发明人： Chin Hui Chong ,  Seng Kim Dalson Ye ,  Hong Wan Ng ,  Kelvin Tan Aik Boo ,  Ling Pan ,  See Hiong Leow

IPC分类号： H01L25/065 ,  H10B80/00

CPC分类号： H01L25/0657 ,  H10B80/00 ,  H01L2225/06506

摘要： A microelectronic device includes a controller device, a first die vertically overlying the controller device, a second die vertically overlying the first die, and a wire. The first die includes a first pad horizontally separated from a horizontal center of the controller device by a first distance. The second die includes a second pad horizontally separated from the horizontal center of the controller device by a second distance larger than the first distance. The wire contacts the first pad of the first die and the second pad of the second die. Memory device packages and electronic systems are also disclosed.

公开(公告)号：US20240074048A1

公开(公告)日：2024-02-29

申请号：US17894070

申请日：2022-08-23

申请人： Micron Technology, Inc.

发明人： Ling Pan ,  Hong Wan Ng ,  Kelvin Tan Aik Boo ,  Seng Kim Ye ,  See Hiong Leow

IPC分类号： H05K1/11 ,  H01L23/00 ,  H01L25/065 ,  H05K1/18 ,  H05K3/46

CPC分类号： H05K1/111 ,  H01L24/16 ,  H01L25/0657 ,  H05K1/181 ,  H05K3/4644 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16237 ,  H01L2225/0652 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/10159 ,  H05K2201/10734

摘要： A semiconductor device assembly includes a semiconductor die, a substrate carrying the semiconductor die, and a printed circuit board (PCB) coupled to the substrate. The PCB includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. The substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. The substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the first solder mask layer through the primary layer to the bond pad of the inner layer. By attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.

公开(公告)号：US20240039185A1

公开(公告)日：2024-02-01

申请号：US17815917

申请日：2022-07-28

申请人： Micron Technology, Inc.

发明人： Wei Yu ,  Ling Pan

IPC分类号： H01R12/52 ,  H01R12/73 ,  H01R12/71

CPC分类号： H01R12/523 ,  H01R12/737 ,  H01R12/718

摘要： Methods, systems, and devices for connection designs for memory systems are described. A memory system may include a package and a printed circuit board (PCB). An interface of the package may be coupled with the PCB via a set of springs, where each spring may include a material configured to deform based at least in part on a shape of the package, a shape of the PCB, or both. The memory system may also include a set of latches that may secure the package in a fixed position relative to the PCB. That is, the set of springs may provide an electrical connection between the package and the PCB, and the set of latches may provide a mechanical connection between the package and the PCB. In some examples, the package, the PCB, or both, may include one or more connection structures configured to receive the latches.

公开(公告)号：US20240312890A1

公开(公告)日：2024-09-19

申请号：US18443166

申请日：2024-02-15

申请人： Micron Technology, Inc.

发明人： Kelvin Tan Aik Boo ,  Hong Wan Ng ,  See Hiong Leow ,  Ling Pan ,  Seng Kim Ye ,  Chin Hui Chong

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/49838 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2924/181 ,  H01L2924/19011

摘要： At least one embodiment of a semiconductor device assembly include a cross-stack substrate can comprise an assembly substrate including an upper surface, a first and second die stack at the upper surface, and a cross-stack substrate spaced from the upper surface. The first and second die stacks can each include multiple semiconductor dies in electric communication with the assembly substrate, and the cross-stack substrate can be coupled to and extending between a first and a second semiconductor die of the first and second die stacks, respectively. A passive semiconductor component can be carried by the cross-stack substrate, and can be in electric communication with the assembly substrate. Further, the passive semiconductor component can be in electric communication with the first semiconductor die of the first die stack exclusively via the assembly substrate.

公开(公告)号：US20240071990A1

公开(公告)日：2024-02-29

申请号：US17896030

申请日：2022-08-25

申请人： Micron Technology, Inc.

发明人： Kelvin Tan Aik Boo ,  Seng Kim Ye ,  Hong Wan Ng ,  Ling Pan ,  See Hiong Leow

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L24/81 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13082 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/1318 ,  H01L2224/13181 ,  H01L2224/13183 ,  H01L2224/13184 ,  H01L2224/16238 ,  H01L2224/81385 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81469 ,  H01L2224/81473 ,  H01L2224/81476 ,  H01L2224/81478 ,  H01L2224/8148 ,  H01L2224/81481 ,  H01L2224/81483 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2924/3841

摘要： A semiconductor device assembly including a semiconductor device having a plurality of pillars disposed on a backside surface of the semiconductor device; and a substrate, including: a solder mask layer disposed on a front side surface of the substrate, a plurality of extended bond pads disposed on the frontside surface of the substrate and surrounded by the solder mask layer, the plurality of extended bond pads each having a top surface higher than a top surface of the solder mask layer, and wherein the semiconductor device is directly attached to the substrate by bonding each of the plurality of pillars of the semiconductor device to the top surface of a corresponding one of the plurality of extended bond pads with a solder connection.

公开(公告)号：US20240071869A1

公开(公告)日：2024-02-29

申请号：US17894102

申请日：2022-08-23

申请人： Micron Technology, Inc.

发明人： Hong Wan Ng ,  Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Ling Pan ,  See Hiong Leow

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L23/481 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/5283

摘要： A semiconductor device assembly including a substrate; a first split via including a first via land that is disposed on a surface of the substrate and that has a first footprint with a half-moon shape with a first radius of curvature, and a first via that passes through the substrate and that has a second radius of curvature, wherein the first via is disposed within the first footprint; and a second split via including a second via land that is disposed on the surface of the substrate and that has a second footprint with the half-moon shape with the first radius of curvature, and a second via that passes through the substrate and that has the second radius of curvature, wherein the second via is disposed within the second footprint, wherein the first and second via lands are disposed entirely within a circular region having the first radius of curvature.

公开(公告)号：US20240234390A1

公开(公告)日：2024-07-11

申请号：US18389613

申请日：2023-12-19

申请人： Micron Technology, Inc.

发明人： Seng Kim Dalson Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng ,  See Hiong Leow ,  Ling Pan

IPC分类号： H01L25/16 ,  H01L23/498

CPC分类号： H01L25/16 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/48

摘要： A microelectronic device package includes a stack of semiconductor dies positioned over a substrate. The microelectronic device package further includes an interposer structure coupled to the stack of semiconductor dies. The microelectronic device package further includes an electronic component directly coupled to the interposer structure and electrically coupled to the substrate through an electrical connection between the interposer structure and the substrate.