公开(公告)号：US20130292810A1

公开(公告)日：2013-11-07

申请号：US13933294

申请日：2013-07-02

Applicant: Micron Technology, Inc.

Inventor： Choon Kuan Lee ,  David J. Corisis ,  Chong Chin Hui

IPC: H05K1/11 ,  H01L23/495

CPC classification number: H05K1/113 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/48 ,  H01L24/82 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/30107 ,  Y10T29/49156 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane.

Abstract translation: 芯片级片上基板或再分配元件的制造方法包括在基板的相对侧上形成导电平面。 导电平面中的第一个包括两组键合指状物，从第一组键合指状物延伸的导电迹线和两组再分布的键合焊盘，包括导电迹线引导到的第一组。 第二导电平面包括从与第二组键合指状物相对的位置朝向与第二组再分布接合焊盘的位置相反的位置延伸的导电迹线。 导电通孔通过第二组接合指形成到第二导电平面的导电迹线。 此外，还形成导电通孔，以将第二导电平面的导电通孔与第一导电平面中相应的再分布接合焊盘电连接。

公开(公告)号：US08749050B2

公开(公告)日：2014-06-10

申请号：US13933294

申请日：2013-07-02

Applicant: Micron Technology, Inc.

Inventor： Choon Kuan Lee ,  David J. Corisis ,  Chong Chin Hui

IPC: H01L23/04

CPC classification number: H05K1/113 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/48 ,  H01L24/82 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/30107 ,  Y10T29/49156 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane.

Abstract translation: 芯片级片上基板或再分配元件的制造方法包括在基板的相对侧上形成导电平面。 导电平面中的第一个包括两组键合指状物，从第一组键合指状物延伸的导电迹线和两组再分布的键合焊盘，包括导电迹线引导到的第一组。 第二导电平面包括从与第二组键合指状物相对的位置朝向与第二组再分布接合焊盘的位置相反的位置延伸的导电迹线。 导电通孔通过第二组接合指形成到第二导电平面的导电迹线。 此外，还形成导电通孔，以将第二导电平面的导电通孔与第一导电平面中相应的再分布接合焊盘电连接。