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公开(公告)号：US11183260B1
公开(公告)日：2021-11-23
申请号：US17098865
申请日：2020-11-16
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Dave Jefferson , Jason M. Johnson , Vivek Kotti , Minoru Someya , Toru Ishikawa , Kevin G. Werhane
Abstract: Memory devices are disclosed. A memory device may include a number of fuses and a number of transmit lines configured to transmit data from the number of fuses. The memory device may also include a number of monitoring circuits. Each monitoring circuit of the number of monitoring circuits is coupled to a transmit line of the number of transmit lines. Each monitoring circuit comprises logic configured to receive the data from the number fuses via the transmit line. The logic is further configured to generate a result responsive to the data and indicative of pass/fail status of the transmit line. Associated methods and systems are also disclosed.
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公开(公告)号：US10930327B1
公开(公告)日：2021-02-23
申请号：US16773824
申请日：2020-01-27
Applicant: Micron Technology, Inc.
Inventor： Dave Jefferson , C. Omar Benitez , Yoshinori Fujiwara , Christopher S. Wieduwilt , Vivek Kotti , Dennis G. Montierth , Joshua E. Alzheimer , Daniel S. Miller , Kevin G. Werhane , Jason M. Johnson
Abstract: Methods, systems, and devices for memory read masking are described. In some cases, a portion of a memory device, such as a portion of a memory array, may be disabled. During a testing operation, a command for accessing one or more memory cells of the disabled portion may be received, and the associated memory cells may be attempted to be accessed. Based on attempting to access the disabled memory cells, a logic state of the disabled cells may be masked. Outputting the masked value may indicate (e.g., to a testing device) that the disabled cells pass the test (e.g., that the memory cells are valid), which may allow for the enabled memory cells and the disabled memory cells of the memory device to be tested using a single test mode.
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